Fabrication process for a static induction transistor

Abstract

A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N - substrate. A P + layer is formed on the underside of the N - substrate. P + -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N + substrate. The N - substrate and the N + substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N - substrate and the N + substrate are heated at about 350° C. in a hydrogen atmosphere in a state that the tops of the projections between the recesses have been brought into contact with the metal layer provided on the underside of the N + substrate, whereby the N - substrate and the N + substrate are joined to each other.

What is claimed is: 
     
       1. A process for fabricating a semiconductor device, which comprises the steps of: providing first and second semiconductor substrates of the same conductive type;   selectively forming gate regions composed of a semiconductor having a conductive type different from that of the first semiconductor substrate in one principal surface of the first semiconductor substrate with portions of said one principal surface of the first semiconductor substrate exposed between the gate regions;   forming a metal layer and/or a metal silicide layer on at least one of at least regions of one principal surface of the second semiconductor substrate, to which portions of said one principal surface of the first semiconductor substrate exposed between the gate regions are opposite, and said one principal surface portions of the first semiconductor substrate exposed between the gate regions; and   joining said one principal surface of the first semiconductor substrate to said one principal surface of the second semiconductor substrate through the metal layer and/or the metal silicide layer.   
     
     
       2. The process according to claim 1, wherein the step of forming the metal layer and/or the metal silicide layer on at least one of at least regions of said one principal surface of the second semiconductor substrate, to which said one principal surface portions of the first semiconductor substrate exposed between the gate regions are opposite, and said one principal surface portions of the first semiconductor substrate exposed between the gate regions is a step of forming the metal layer and/or the metal silicide layer on at least the regions of said one principal surface of the second semiconductor substrate, to which said one principal surface portions of the first semiconductor substrate exposed between the gate regions are opposite. 
     
     
       3. The process according to claim 2, wherein the step of forming the metal layer and/or the metal silicide layer on at least one of at least regions of said one principal surface of the second semiconductor substrate, to which said one principal surface portions of the first semiconductor substrate exposed between the gate regions are opposite, and said one principal surface portions of the first semiconductor substrate exposed between the gate regions is a step of forming the metal layer and/or the metal silicide layer on the whole principal surface of the second semiconductor substrate. 
     
     
       4. The process according to claim 1, wherein the step of selectively forming the gate regions composed of the semiconductor having the conductive type different from that of the first semiconductor substrate in said one principal surface of the first semiconductor substrate with portions of said one principal surface of the first semiconductor substrate exposed between the gate regions is a step of defining recesses in said one principal surface of the first semiconductor substrate in such a manner that said one principal surface of the first semiconductor substrate is partly exposed between the recesses to separately provide the gate regions in at least regions exposed on sides of the recesses defined in the first semiconductor substrate. 
     
     
       5. The process according to claim 1, wherein the step of selectively forming the gate regions composed of the semiconductor having the conductive type different from that of the first semiconductor substrate in said one principal surface of the first semiconductor substrate with portions of said one principal surface of the first semiconductor substrate exposed between the gate regions is a step of defining recesses in said one principal surface of the first semiconductor substrate in such a manner that said one principal surface of the first semiconductor substrate is partly exposed between the recesses to separately provide the gate regions in at least regions exposed on the bottoms of the recesses defined in the first semiconductor substrate. 
     
     
       6. The process according to claim 1, wherein an insulating film covering each of the gate regions is selectively provided while leaving said one principal surface portions of the first semiconductor substrate exposed between the gate regions intact, the metal layer and/or the metal silicide layer is formed on said one principal surface portions of the first semiconductor substrate exposed between the gate regions if the metal layer and/or the metal silicide layer is formed on said one principal surface portions, and said one principal surface of the first semiconductor substrate is then joined to said one principal surface of the second semiconductor substrate. 
     
     
       7. The process according to claim 2, wherein an insulating film covering each of the gate regions is selectively provided while leaving said one principal surface portions of the first semiconductor substrate exposed between the gate regions intact, and said one principal surface of the first semiconductor substrate is then joined to said one principal surface of the second semiconductor substrate through the metal layer and/or the metal silicide layer, whereby said one principal surface of the first semiconductor substrate is electrically connected to said one principal surface of the second semiconductor substrate through the metal layer and/or the metal silicide layer. 
     
     
       8. The process according to claim 1, wherein an insulating film covering each of the gate regions is selectively provided while leaving said one principal surface portions of the first semiconductor substrate exposed between the gate regions intact, the metal layer and/or the metal silicide layer is formed on said one principal surface portions of the first semiconductor substrate exposed between the gate regions, and said one principal surface of the first semiconductor substrate is then joined to said one principal surface of the second semiconductor substrate. 
     
     
       9. The process according to claim 8, wherein the metal layer and/or the metal silicide layer is also formed on at least regions of said one principal surface of the second semiconductor substrate, to which said one principal surface portions of the first semiconductor substrate exposed between the gate regions are opposite. 
     
     
       10. The process according to claim 1, which further comprises the step of providing a semiconductor region, which has the same conductive type as that of the first semiconductor substrate and is higher in impurity concentration than the first semiconductor substrate. 
     
     
       11. The process according to claim 4, wherein a conductive gate electrode electrically connected to each of the gate regions is provided within the recess, and said one principal surface of the first semiconductor substrate is then joined to said one principal surface of the second semiconductor substrate. 
     
     
       12. The process according to claim 11, which further comprises the step of providing a protective film covering the gate electrode within the recess. 
     
     
       13. The process according to claim 1, wherein the second semiconductor substrate is a semiconductor substrate higher in impurity concentration than the first semiconductor substrate. 
     
     
       14. The process according to claim 1, wherein the conductive type of the first and second semiconductor substrates is of n-type, and the metal is an Au-Sb alloy. 
     
     
       15. The process according to claim 1, which further comprises the steps of: forming the first layer of a semiconductor having the different conductive type on any one of the other principal surface opposite to said one principal surface of the first semiconductor substrate and the other principal surface opposite to said one principal surface of the second semiconductor substrate;   providing one of an anode and a cathode on the other principal surface of the first semiconductor substrate or the first semiconductor layer so as to electrically connect to each other; and   providing the other of the anode and the cathode on the other principal surface of the second semiconductor substrate or the first semiconductor layer so as to electrically connect to each other.