Process of fabricating dynamic random access memory device having storage capacitor low in contact resistance and small in leakage current through tantalum oxide film

Abstract

When tantalum oxide is used for a dielectric film of a stacked type storage capacitor forming a memory cell together with a switching transistor, heat treatments are limited to 530 degrees centigrade in the stages after the deposition of the tantalum oxide, and leakage current across the tantalum oxide is drastically decreased.

What is claimed is: 
     
       1. A process of fabricating a semiconductor dynamic random access memory device, comprising the steps of: a) preparing a semiconductor substrate including a first area assinged to a plurality of memory cells and a second area assigned to peripheral circuits, at least one complementary transistor being incorproated in said peripehral circuits;   b) fabricating switching transistors of said plurality of memory cells and said at least one complementary transistor on said semiconductor substrate;   c) covering said switching transistors and said at least on complementary transistor with a lower inter-level insulating structure having first contact holes exposing first impurity regions of said switching transistors;   d) fabricating storage capacitors having respective storage node electrodes respectively held in contact through said first contact holes with said first impurity regions, dielectric films of tantalum oxide covering said storage node electrodes and at least one cell plate electrode held in contact with said dielectric films so as to be opposed to said storage node electrodes; and   e) covering said storage capacitors with an upper inter-level insulating structure having second contact holes exposing second impurity regions of said at least one complementary transistor by using a deposition technique carried out at a first temperature equal to or less than 530 degrees centigrade; and   f) forming at least one interconnection on said upper inter-level insulating structure connected through said second contact holes with said second impurity regions by using techniques carried out at second temperatures not greater than 530 degrees centigrade.   
     
     
       2. The process as set forth in claim 1, in which said step f) includes the sub-steps of f-1) covering said second impurity regions with protective layers,   f-2) ion implanting a dopant impurity of a first conductivity type and another dopant impurity of a second conductivity type opposite to said first conductivity type so as to form at least one first amorphous ion-implanted sub-region of said first conductivity type in one of said second impurity regions of said first conductivity type and at least one second amorphous ion-implanted sub-region of sid second conductivity type in another of said second impurity regions of said second conductivity type,   f-3) removing said protective layers,   f-4) covering said one of said second impurity regions and said another of said second impurity regions exposed to said second contact holes with first refractory metal layers,   f-5) heating said first refractory metal layers to a temperature between 470 degrees centigrade and 530 degres centigrade in an inert atmosphere so as to convert at least parts of said first refractory metal layers into refractory metal silicide layers, and   f-6) forming remaining parts of siad at least one interconnection.   
     
     
       3. The process as set forth in claim 2, in which said dopant impurity and said another dopant impurity are phosphorous and boron fluoride, respectively, said second impurity regions have respective p-n junctions around 0.15 microns in depth, said protective layers are 10 nanoters thick, and said first refractory metal layers are 40 to 50 nanometers thick; said dopnat impurity being ion-implanted under the following conditions,   when the acceleration energy is 10 KeV, a dose of said phosphorous has the lower limit equal to or greater than 10 13  cm -2  and the upper limit equal to or less than 10 16  cm -2  ;   when the acceleration energy is 30 KeV, said dose of said phosphorous has the lower limit equal to or greater than 10 13  cm -2  and the upper limit equal to or less than 10 16  cm -2  ; or   when the acceleration energy is 70 KeV, said dose of said phosphorous has the lower limit equal to or greater than 10 13  cm -2  and the upper limit equal to or less than 4×10 15  cm -2  ;   said another dopant impurity being ion implanted under the following conditions,   when the acceleration energy is 10 KeV, a dose of said boron fluoride has the lower limit equal to or greater than 3×10 13  cm -2  and the upper limit equal to or less than 3×10 16  cm -2 ,   when the acceleration energy is 30 KeV, said dose of said boron fluoride has the lower limit equal to or greater than 3×10 13  cm -2  and the upper limit equal to or less than 3×10 16  cm -2 ,   when the acceleration energy is 70 KeV, said dose of said boron fluoride has the lower limit equal to or greater than 3×10 13  cm -2  and the upper limit equal to or less than 3×10 15  cm -2 , or   when the acceleration energy is 100 KeV, said dose of said boron fluoride has the lower limit equal to or greater than 3×10 13  cm -2  and the upper limit equal to or less than 1×10 15  cm -2 .   
     
     
       4. The process as set forth in claim 2, in which said second impurity regions are formed of silicon, and said first refractory metal layers are formed of titanium. 
     
     
       5. The process as set forth in claim 2, in which said sub-step f-6) has the sub-steps of f-6-1) plugging said second contact holes with pieces of second refractory metal,   f-6-2) depositing a conductive material layer on said upper inter-level insulating structure, and   f-6-3) patterning said conductive material layer into a wiring.   
     
     
       6. The process as set forth in claim 1, in which said step c) includes the sub-steps of c-1) depositing a first non-doped silicon oxide layer over said switching transistors and said at least on complementary transistor through a low-pressure chemical vapor deposition in a first gaseous mixture containing tetraethylorthosilicate gas,   c-2) smoothening an upper surface of said first non-doped silicon oxide layer where bit lines connected through selected ones of said first contact holes to said switching transistors extends for said switching transistors,   c-3) depositing a second non-doped silicon oxide layer over said upper surface of said first non-doped silicon layer, and   c-4) smoothening an upper surface of said second non-doped silicon oxide layer where said storage capacitors connected through others of said first contact holes to said switching transistors are formed.   
     
     
       7. The process as set forth in claim 6, in which one of an etch-back and a chemical-mechanical polishing is used in said sub-steps c-2) and c-4). 
     
     
       8. The process as set forth in claim 1, in which said step d) includes the sub-steps of d-1) forming said storage node electrodes on said upper surface of said lower inter-level insulating structure,   d-2) depositing a tantalum oxide layer on said storage node electrodes by using an reaction of ethoxy tantalum with oxygen around 450 degrees centigrade,   d-3) depositing a titanium nitride layer on said tantalum oxide layer by using a reactive sputtering,   d-4) depositing tungsten silicide layer on said titanium nitride layer by using a sputtering, and   d-5) patterning said tungsten silicide layer, said titanium nitride layer and said tantalum oxide layer into said dielectric films of said tantalum oxide and said at least one cell plate electrode.   
     
     
       9. The process as set forth in claim 1, in which said step e) includes the sub-steps of e-1) depositing a first non-doped silicon oxide layer over said storage capacitors and said lower inter-level insulating structure by using a plasma-exited chemical vapor deposition at a temperature lower than 500 degrees centigrade,   e-2) coating said first non-doped silicon oxide layer with a spin-on-glass layer of silicon oxide,   e-3) baking said spin-on-glass layer around 400 degrees centigrade, and   e-4) depositing a second non-doped silicon oxide layer over said spin-on-glass layer by using said plasma-exited chemical vapor deposition at a temperature lower than 500 degrees centigrade.   
     
     
       10. The process as set forth in claim 9, said step e) further including the sub-step of smoothening an upper surface of said spin-on-glass layer between said sub-step e-3) and said sub-step e-4).