Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure

Abstract

A semiconductor fabrication process, allowing integration of MOSFET devices, and capacitor structures, on a single semiconductor chip, has been developed. The process integration features the use of a MOSFET device, fabricated using a self-aligned contact structure, allowing a reduction in the source and drain area needed for contact. Silicon nitride spacers, used on the sides of the polysilicon gate electrode, protect the polysilicon gate structure, during the opening of a self-aligned contact hole.

What is claimed is: 
     
       1. A fabrication procedure for integrating a MOSFET device, and of a capacitor structure, on a semiconductor substrate, comprising the steps of: forming field oxide regions in said semiconductor substrate;   forming an N well region, in an area of said semiconductor substrate, to be used for said MOSFET device;   growing a gate insulator layer on said semiconductor substrate;   depositing a polysilicon layer on said FOX regions, and on said gate insulator layer;   doping of said polysilicon layer;   growing a capacitor silicon oxide layer on said polysilicon layer;   depositing a capacitor silicon nitride layer on said capacitor silicon oxide layer;   depositing a first silicon oxide layer on said capacitor silicon nitride layer;   patterning to create a polysilicon gate structure, on said gate insulator layer, comprised of said first silicon oxide layer, said capacitor silicon nitride layer, said capacitor silicon oxide layer, and said polysilicon layer;   patterning to create a polysilicon gate, contact structure, on a first FOX region, comprised of said first silicon oxide layer, said capacitor silicon nitride layer, said capacitor silicon oxide layer, and said polysilicon layer;   patterning to create a lower electrode shape, for said capacitor structure, on a second FOX region, comprised of said first silicon oxide layer, said capacitor silicon nitride layer, said capacitor silicon oxide layer, and said polysilicon layer;   growing a thin sidewall silicon oxide layer, on the exposed polysilicon sides of said polysilicon gate structure, on said gate insulator layer, on the exposed polysilicon sides of said polysilicon gate, contact structure, on said first FOX region, and on exposed polysilicon sides of said lower electrode shape;   depositing a sidewall silicon nitride layer;   anisotropic etching of said sidewall silicon nitride layer to create silicon nitride spacers on the sides of said polysilicon gate structure, on said gate insulator layer, on the sides of said polysilicon gate, contact structure, on said first FOX region, and on the sides of said lower electrode shape;   ion implanting a first conductivity imparting dopant, into a region of said semiconductor substrate, not covered by said FOX regions, and not covered by said polysilicon gate structure, to form source and drain regions for said MOSFET device;   depositing an interlevel dielectric layer, comprised of an underlying, undoped silicon oxide layer, and an overlying, doped silicon oxide layer;   planarizing said interlevel dielectric layer;   opening a self-aligned contact, (SAC), hole, in said interlevel dielectric layer, with said SAC opening exposing an area of said source and drain region, and partially extended over said polysilicon gate structure, of said MOSFET device;   opening a hole in said interlevel dielectric layer, and in said first silicon oxide layer, exposing said capacitor silicon nitride layer, overlying said lower electrode shape, defining an area for an upper electrode shape, for said capacitor structure;   opening a contact hole in said interlevel dielectric layer, in said first silicon oxide layer, in said capacitor silicon nitride layer, and in said capacitor silicon oxide layer, exposing top surface of said polysilicon layer, of said polysilicon gate, contact structure;   depositing a metal layer;   patterning of said metal layer, forming a self-aligned contact structure, in said SAC hole, contacting underlying, said source and drain regions, of said MOSFET device;   patterning of said metal layer, forming a metal contact structure, to top surface of said polysilicon layer, of said polysilicon gate, contact structure, on said first FOX region; and   patterning of said metal layer, forming an upper electrode shape for said capacitor structure.   
     
     
       2. The method of claim 1, wherein said gate insulator layer is silicon dioxide, thermally grown in an oxygen--steam ambient, at a temperature between about 850° to 1000° C., to a thickness between about 50 to 200 Angstroms. 
     
     
       3. The method of claim 1, wherein said polysilicon layer is deposited using LPCVD procedures, at a temperature between about 550° to 650° C., to a thickness between about 2000 to 4000 Angstroms. 
     
     
       4. The method of claim 1, wherein said capacitor silicon oxide layer is thermally grown, in an oxygen--steam ambient, at a temperature between about 850° to 950° C., to a thickness between about 50 to 250 Angstroms. 
     
     
       5. The method of claim 1, wherein said capacitor silicon nitride layer is deposited using LPCVD or PECVD procedures, at a temperature between about 700° to 850° C., to a thickness between about 200 to 1000 Angstroms. 
     
     
       6. The method of claim 1, wherein said sidewall silicon nitride layer is deposited using LPCVD or PECVD procedures, at a temperature between about 700° to 850° C., to a thickness between about 1000 to 3000 Angstroms. 
     
     
       7. The method of claim 1, wherein said silicon nitride spacers are formed via anisotropic RIE of said sidewall silicon nitride layer, using SF 6  or CHF 3  as an etchant. 
     
     
       8. The method of claim 1, therein said first conductivity imparting dopant is B 11  or BF 2 , ion implanted at an energy between about 20 to 40 KeV, at a dose between about 8E14 to 6E15 atoms/cm 2 . 
     
     
       9. The method of claim 1, wherein said interlevel dielectric layer is comprised of an underlying layer of said undoped, silicon oxide, and an overlying layer of said doped silicon oxide, with said doped silicon oxide comprised of boro-phosphosilicate glass, deposited using PECVD procedures, at a temperature between about 300° to 500° C., to a thickness between about 3000 to 10000 Angstroms. 
     
     
       10. The method of claim 1, wherein said SAC opening, is created via anisotropic RIE procedures, using CHF 3  as an etchant, with said SAC opening having a diameter between about 0.50 to 3.0 μM. 
     
     
       11. The method of claim 1, wherein region for said upper electrode shape, for said capacitor structure, is opened via initial etching of said interlevel dielectric layer, using anisotropic RIE procedures, using CHF 3  as an etchant, and completed by using a buffered hydrofluoric acid solution to etch said first silicon oxide layer. 
     
     
       12. The method of claim 1, wherein said SAC structure, and said upper electrode shape, are comprised of an underlying layer of titanium--titanium nitride, and an overlying layer of aluminum, containing between about 1 to 3% copper, and between about 0.5 to 2% silicon. 
     
     
       13. A fabrication process for integrating a MOSFET device and a capacitor structure, on a semiconductor substrate, with said MOSFET device having a self-aligned contact structure to source and drain regions, and having silicon nitride spacers, on the sides of a polysilicon gate structure, comprising the steps of: forming field oxide regions in said semiconductor substrate;   forming an N well region in an area of said semiconductor substrate, to be used for said MOSFET device;   growing a silicon dioxide gate insulator layer on said semiconductor substrate;   depositing a polysilicon layer on said silicon dioxide gate insulator layer, and on said FOX regions;   doping said polysilicon layer;   depositing a first silicon oxide layer on said polysilicon layer;   removing said first silicon oxide region from said polysilicon layer, in a region wherein said capacitor structure is to be formed, while leaving said first silicon oxide layer, on said polysilicon layer, in a region in which said MOSFET device is to be formed;   patterning of said first silicon oxide layer, and of said polysilicon layer, to create a polysilicon gate structure, for said MOSFET device, on said silicon oxide gate insulator layer;   patterning of said polysilicon layer to create a lower electrode shape, for said capacitor structure, on said field oxide region;   growing a thin sidewall silicon oxide layer on the exposed polysilicon sides of said polysilicon gate structure, and on the exposed polysilicon sides of said lower electrode shape, for said capacitor structure;   depositing a sidewall silicon nitride layer;   anisotropic etching of said sidewall silicon nitride layer, to form said silicon nitride spacers on the sides of said polysilicon gate structure, of said MOSFET device, and to form said silicon nitride spacers on the sides of said lower electrode shape, for said capacitor structure;   growing a silicon oxide capacitor layer, on the top surface of said lower electrode shape;   ion implanting a first conductivity imparting dopant into a region of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said FOX regions, to create source and drain regions, for said MOSFET device;   depositing a silicon nitride capacitor layer;   depositing an interlevel dielectric layer, on said silicon nitride capacitor layer, with said interlevel dielectric layer comprised of an underlying, undoped silicon oxide layer, and an overlying layer of doped silicon oxide;   planarizing said interlevel dielectric layer;   opening a hole in said interlevel dielectric layer, exposing said silicon nitride capacitor layer, overlying said lower electrode shape, defining an area for an upper electrode shape, for said capacitor structure;   opening a self-aligned contact, (SAC), hole, in said interlevel dielectric layer, and in said silicon nitride capacitor layer, to expose said source and drain region, with said SAC hole partially extending over said polysilicon gate structure;   depositing a metal layer;   patterning of said metal layer, forming said SAC structure, in said SAC hole, contacting said source and drain region, of said MOSFET device; and   patterning of said metal layer, forming said upper electrode shape, for said capacitor structure.   
     
     
       14. The method of claim 13, wherein said silicon dioxide gate insulator layer is thermally grown, in an oxygen steam ambient, at a temperature between about 850° to 1000° C., to a thickness between about 50 to 200 Angstroms. 
     
     
       15. The method of claim 13, wherein said polysilicon layer is deposited using LPCVD procedures, at a temperature between about 550° to 650° C., to a thickness between about 2000 to 4000 Angstroms. 
     
     
       16. The method of claim 13, wherein said sidewall silicon nitride layer is deposited using LPCVD or PECVD procedures, at a temperature between about 700° to 850° C., to a thickness between about 200 to 1000 Angstroms. 
     
     
       17. The method of claim 13, wherein said silicon nitride spacers are created via anisotropic RIE of said sidewall silicon nitride layer, using SF 6  or CHF 3  as an etchant. 
     
     
       18. The method of claim 13, wherein said silicon oxide capacitor layer is thermally grown, at a temperature between about 850° to 950° C., to a thickness between about 50 to 250 Angstroms. 
     
     
       19. The method of claim 13, wherein said first conductivity imparting dopant, used to form said source and drain regions, is B 11  of BF 2 , ion implanted at an energy between about 20 to 40 KeV, at a dose between about 8E14 to 6E15 atoms/cm 2 . 
     
     
       20. The method of claim 13, wherein said silicon nitride capacitor layer is deposited via LPCVD or PECVD procedures, at a temperature between about 700° to 850° C., to a thickness between about 200 to 1000 Angstroms. 
     
     
       21. The method of claim 13, wherein said interlevel dielectric layer, is deposited using PECVD procedures, at a temperature between about 300° to 500° C., to a thickness between about 3000 to 10000 Angstroms, and is comprised of an underlying, said undoped silicon oxide layer, and an overlying layer of boro-phosphosilicate glass. 
     
     
       22. The method of claim 13, wherein said SAC hole is created via buffered hydrofluoric acid, wet etching of said interlevel dielectric layer, and anisotropic RIE of said silicon nitride capacitor layer, using SF 6  as an etchant, with said SAC hole having a diameter between about 1.0 to 5.0 μM. 
     
     
       23. The method of claim 13, wherein hole in said interlevel dielectric layer, defining the space for said upper electrode shape, is created via a buffered hydrofluoric acid wet etch procedure. 
     
     
       24. The method of claim 1, wherein said SAC structure, of said MOSFET device, and said upper electrode shape, of said capacitor structure, are comprised of an underlying titanium--titanium nitride layer, and an overlying layer of an aluminum based metal, containing between about 1 to 3% copper, and between about 0.5 to 2% silicon.