Method of forming dram circuitry on a semiconductor substrate

Abstract

A method of forming DRAM circuitry includes, a) defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of second conductivity type transistors; b) providing a plurality of patterned gate lines within the array area and the peripheral area, the gate lines defining respective source areas and drain areas adjacent thereto; c) providing capacitor storage nodes over selected array source areas; d) providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the storage nodes and the peripheral area; and e) in two separate photomasking and two separate etching steps, etching the cell plate layer to substantially remove cell plate material from the peripheral area and provide bit line contact openings through the cell plate layer to selected drains in the array area. The method further includes, in two separate photomasking and two separate etching steps, collectively a) etching the capacitor cell plate layer to substantially remove cell plate material from the NMOS peripheral area and thereafter doping the NMOS peripheral area with n-type material, and b) etching the capacitor cell plate layer to substantially remove cell plate material from the PMOS peripheral area and thereafter doping the PMOS peripheral area with p-type material.

I claim: 
     
       1. A method of forming DRAM circuitry on a semiconductor substrate having complementary metal oxide semiconductor field effect transistors and associated capacitors comprising the following steps: defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of first and second conductivity type CMOS field effect transistors, the peripheral area comprising first and second peripheral areas, the first and second conductivity type transistors to be formed in the first and second peripheral areas, respectively;   providing a plurality of patterned gate lines within the memory array area, the first peripheral area and the second peripheral area; the gate lines defining respective source areas and drain areas adjacent thereto;   providing an insulating dielectric layer within the array area and the first and second peripheral areas over the gate lines, the source areas and the drain areas;   patterning and etching the insulating dielectric layer to outwardly expose selected source areas within the array area;   providing an electrically conductive capacitor storage node layer over the patterned insulating dielectric layer;   patterning and etching the capacitor storage node layer to define respective capacitor storage nodes over the selected array source areas, the storage node etching not going completely through the insulating dielectric layer;   providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the capacitor storage nodes and the first and second peripheral areas;   first photomasking the cell plate layer to cover the array storage nodes and to cover the second peripheral area, while leaving selected source or areas within the array and the first peripheral area unmasked;   with the first photomasking in place, first etching the capacitor cell plate layer and insulating dielectric layer to effectively expose the selected array drain areas and the first peripheral area;   after effectively exposing the selected array drain areas and the first peripheral area source and drain areas and with the first photomasking still in place, implanting first conductivity type dopant impurity into the selected array drain areas and the first peripheral area to form conductively doped array drain regions and conductively doped first peripheral area source and drain regions;   second photomasking the array area and the first peripheral area while leaving the second peripheral area exposed;   with the second photomasking in place, second etching the capacitor cell plate layer and the capacitor dielectric layer from the second peripheral area; and   with the second photomasking in place and after the second etching of the capacitor cell layer, implanting second conductivity type dopant impurity into the source areas and the drain areas in the second peripheral area to form conductively doped second peripheral area drain and source regions.   
     
     
       2. The method of forming DRAM circuitry of claim 1 wherein the insulating dielectric layer comprises oxide. 
     
     
       3. The method of forming DRAM circuitry of claim 1 wherein the insulating dielectric layer comprises a composite of at least two separately deposited layers. 
     
     
       4. The method of forming DRAM circuitry of claim 1 wherein the insulating dielectric layer comprises a composite of at least two separately deposited layers, the separately deposited layers comprising the same predominate material. 
     
     
       5. The method of forming DRAM circuitry of claim 1 wherein, the insulating dielectric layer comprises a composite of at least two separately deposited layers; and   the step of etching the capacitor storage node layer comprising substantially etching through one of the two layers but substantially not through the other of the two layers.   
     
     
       6. The method of forming DRAM circuitry of claim 1 wherein the collective steps of, a) first and second etching the capacitor cell plate, b) first conductivity type implanting, and c) second conductivity type implanting are conducted with no more photomasking steps than said first and second photomaskings. 
     
     
       7. The method of forming DRAM circuitry of claim 1 wherein the first conductivity type is n and the second conductivity type is p. 
     
     
       8. The method of forming DRAM circuitry of claim 1 wherein the first conductivity type is p and the second conductivity type is n. 
     
     
       9. The method of forming DRAM circuitry of claim 1 wherein the second masking occurs after the first masking. 
     
     
       10. The method of forming DRAM circuitry of claim 1 wherein the second masking overlaps with a portion of the second peripheral area and thereby a portion of the capacitor cell plate layer and capacitor dielectric layer in the second peripheral area, the second etching step leaving a composite hedge of the capacitor cell plate layer and capacitor dielectric layer relative to an interface of the array area and the second peripheral area. 
     
     
       11. The method of forming DRAM circuitry of claim 1 wherein, the insulating dielectric layer comprises a composite of at least two separately deposited layers; and   the collective steps of, a) first and second etching the capacitor cell plate, b) first conductivity type implanting, and c) second conductivity type implanting are conducted with no more photomasking steps than said first and second photomaskings.   
     
     
       12. The method of forming DRAM circuitry of claim 1 wherein, the insulating dielectric layer comprises a composite of at least two separately deposited layers; and   the capacitor storage node layer comprises first conductivity type dopant material, the conductively doping step consisting essentially of out-diffusion of first conductivity type dopant impurity from the capacitor storage node layer.   
     
     
       13. The method of forming DRAM circuitry of claim 1 wherein, the insulating dielectric layer comprises a composite of at least two separately deposited layers; and   the second masking overlaps with a portion of the second peripheral area and thereby a portion of the capacitor cell plate layer and capacitor dielectric layer in the second peripheral area, the second etching step leaving a composite hedge of the capacitor cell plate layer and capacitor dielectric layer relative to an interface of the array area and the second peripheral area.   
     
     
       14. The method of forming DRAM circuitry of claim 1 wherein, the collective steps of, a) first and second etching the capacitor cell plate, b) first conductivity type implanting, and c) second conductivity type implanting are conducted with no more photomasking steps than said first and second photomaskings; and   the capacitor storage node layer comprises first conductivity type dopant material, the conductively doping step consisting essentially of out-diffusion of first conductivity type dopant impurity from the capacitor storage node layer.   
     
     
       15. The method of forming DRAM circuitry of claim 1 wherein, the collective steps of a) first and second etching the capacitor cell plate, b) first conductivity type implanting, and c) second conductivity type implanting are conducted with no more photomasking steps than said first and second photomaskings; and   the second masking overlaps with a portion of the second peripheral area and thereby a portion of the capacitor cell plate layer and capacitor dielectric layer in the second peripheral area, the second etching step leaving a composite hedge of the capacitor cell plate layer and capacitor dielectric layer relative to an interface of the array area and the second peripheral area.   
     
     
       16. The method of forming DRAM circuitry of claim 1 wherein, the capacitor storage node layer comprises first conductivity type dopant material, the conductively doping step consisting essentially of out-diffusion of first conductivity type dopant impurity from the capacitor storage node layer; and   the second masking overlaps with a portion of the second peripheral area and thereby a portion of the capacitor cell plate layer and capacitor dielectric layer in the second peripheral area, the second etching step leaving a composite hedge of the capacitor cell plate layer and capacitor dielectric layer relative to an interface of the array area and the second peripheral area.   
     
     
       17. The method of forming DRAM circuitry of claim 1 wherein, the insulating dielectric layer comprises a composite of at least two separately deposited layers;   the collective steps of, a) first and second etching the capacitor cell plate, b) first conductivity type implanting, and c) second conductivity type implanting are conducted with no more photomasking steps than said first and second photomaskings; and   the second masking overlaps with a portion of the second peripheral area and thereby a portion of the capacitor cell plate layer and capacitor dielectric layer in the second peripheral area, the second etching step leaving a composite hedge of the capacitor cell plate layer and capacitor dielectric layer relative to an interface of the array area and the second peripheral area.   
     
     
       18. The method of forming DRAM circuitry of claim 1 wherein, the collective steps of, a) first and second etching the capacitor cell plate, b) first conductivity type implanting, and c) second conductivity type implanting are conducted with no more photomasking steps than said first and second photomaskings;   the capacitor storage node layer comprises first conductivity type dopant material, the conductively doping step consisting essentially of out-diffusion of first conductivity type dopant impurity from the capacitor storage node layer; and   the second masking overlaps with a portion of the second peripheral area and thereby a portion of the capacitor cell plate layer and capacitor dielectric layer in the second peripheral area, the second etching step leaving a composite hedge of the capacitor cell plate layer and capacitor dielectric layer relative to an interface of the array area and the second peripheral area.   
     
     
       19. A method of forming DRAM circuitry on a semiconductor substrate having complementary metal oxide semiconductor field effect transistors and associated capacitors comprising the following steps: defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of first and second conductivity type CMOS field effect transistors, the peripheral area comprising first and second peripheral areas, the first and second conductivity type transistors to be formed in the first and second peripheral areas, respectively;   providing a plurality of patterned gate lines within the memory array area, the first peripheral area and the second peripheral area; the gate lines defining respective source areas and drain areas adjacent thereto;   providing an insulating dielectric layer within the array area and the first and second peripheral areas over the gate lines, the source areas and the drain areas;   patterning and etching the insulating dielectric layer to outwardly expose selected source areas within the array area;   providing an electrically conductive capacitor storage node layer over the patterned insulating dielectric layer;   patterning and etching the capacitor storage node layer to define respective capacitor storage nodes over the selected array source areas, the storage node etching stopping relative to the insulating dielectric layer;   providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the capacitor storage nodes and the first and second peripheral areas;   first photomasking the cell plate layer to cover the array storage nodes and to cover the second peripheral area, while leaving the first peripheral area unmasked;   with the first photomasking in place, first etching the capacitor cell plate layer and insulating dielectric layer to effectively expose first peripheral area source and drain areas;   after effectively exposing the first peripheral area source and drain areas and with the first photomasking still in place, implanting first conductivity type dopant impurity into the first peripheral area to form conductively doped first peripheral area source and drain regions;   second photomasking the array area and the first peripheral area while leaving the second peripheral area exposed;   with the second photomasking in place, second etching the capacitor cell plate layer and the capacitor dielectric layer from the second peripheral area; and   with the second photomasking in place and after the second etching of the capacitor cell layer, implanting second conductivity type dopant impurity into the source areas and the drain areas in the second peripheral area to form conductively doped second peripheral area drain and source regions.   
     
     
       20. The method of forming DRAM circuitry of claim 19 wherein the insulating dielectric layer comprises a composite of at least two separately deposited layers. 
     
     
       21. The method of forming DRAM circuitry of claim 19 wherein the insulating dielectric layer comprises a composite of at least two separately deposited layers, the separately deposited layers comprising the same predominate material. 
     
     
       22. The method of forming DRAM circuitry of claim 19 wherein, the insulating dielectric layer comprises a composite of at least two separately deposited layers; and   the step of etching the capacitor storage node layer comprising substantially etching through one of the two layers but substantially not through the other of the two layers.   
     
     
       23. The method of forming DRAM circuitry of claim 19 wherein the collective steps of, a) first and second etching the capacitor cell plate, b) first conductivity type implanting, and c) second conductivity type implanting are conducted with no more photomasking steps than said first and second photomaskings. 
     
     
       24. The method of forming DRAM circuitry of claim 19 wherein the second masking occurs after the first masking. 
     
     
       25. The method of forming DRAM circuitry of claim 19 wherein the second masking overlaps with a portion of the second peripheral area and thereby a portion of the capacitor cell plate layer and capacitor dielectric layer in the second peripheral area, the second etching step leaving a composite hedge of the capacitor cell plate layer and capacitor dielectric layer relative to an interface of the array area and the second peripheral area. 
     
     
       26. A method of forming DRAM circuitry on a semiconductor substrate having complementary metal oxide semiconductor field effect transistors and associated capacitors comprising the following steps: defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of second conductivity type field effect transistors;   providing a plurality of patterned gate lines within the memory array area and the peripheral area the gate lines defining respective source areas and drain areas adjacent thereto;   providing capacitor storage nodes over selected array source areas;   providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the capacitor storage nodes and the peripheral area; and   in two separate photomasking and two separate etching steps, collectively etching the capacitor cell plate layer to substantially remove cell plate material from the peripheral area and provide bit line contact openings through the capacitor cell plate layer to selected drains in the array area.   
     
     
       27. The method of forming DRAM circuitry of claim 26 wherein one of the photomasking and etching steps comprises a single and common masking step utilized in patterning and etching the cell plate layer to effectively outwardly expose selected drain areas within the array and then implanting a conductivity dopant impurity into the selected array drain areas to form electrically conductive drain regions within the substrate in the array area. 
     
     
       28. The method of forming DRAM circuitry of claim 26 further comprising conductively doping array drain areas and peripheral area source and drain areas to form electrically conductive drain regions within the substrate in the array area and electrically conductive source and drain regions in the peripheral area, the conductively doping to form such regions being conducted after provision of the capacitor cell plate layer; and wherein one of the photomasking and etching steps comprises a single and common masking step utilized in patterning and etching the cell plate layer to effectively outwardly expose selected drain areas within the array and then implanting a conductivity dopant impurity into the selected array drain areas to form electrically conductive drain regions within the substrate in the array area.   
     
     
       29. A method of forming DRAM circuitry on a semiconductor substrate having complementary metal oxide semiconductor field effect transistors and associated capacitors comprising the following steps: defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an NMOS peripheral area and a PMOS peripheral area;   providing a plurality of patterned gate lines within the memory array area and the peripheral areas, the gate lines defining respective source areas and drain areas adjacent thereto;   providing capacitor storage nodes over selected array source areas;   providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the capacitor storage nodes and the peripheral areas; and   in two separate photomasking and two separate etching steps, collectively, a) etching the capacitor cell plate layer to substantially remove cell plate material from the NMOS peripheral area and thereafter doping the NMOS peripheral area with n-type material, and b) etching the capacitor cell plate layer to substantially remove cell plate material from the PMOS peripheral area and thereafter doping the PMOS peripheral area with p-type material.   
     
     
       30. The method of forming DRAM circuitry of claim 29 wherein the first conductivity type is n. 
     
     
       31. A method of forming a memory device on a semiconductor substrate, comprising the steps of: providing a structure on a semiconductor substrate, said structure comprising a memory array region having a plurality of memory array gate areas and a plurality of memory array storage nodes, and a periphery region comprising a plurality of periphery gate areas, said structure having a layer of a dielectric material and a layer of conductive material thereon;   forming a first mask over a first portion of said memory array region and over a first portion of said periphery region;   performing a first etch to remove unmasked portions of said conductive material layer and said dielectric layer;   first doping said substrate after said first etch with a dopant;   removing said first mask from said substrate structure;   forming a second mask over at least a second portion of said memory array region;   performing a second etch to remove unmasked portions of said dielectric material layer and said conductive material; and   second doping said substrate with a second dopant.   
     
     
       32. The method of claim 31 wherein said step of performing said second etch further comprises etching an oxide layer beneath said dielectric material layer. 
     
     
       33. The method of claim 31 wherein said step of performing said first etch further comprises etching an oxide layer beneath said dielectric material layer. 
     
     
       34. The method of claim 31 wherein said first and second mask portions have areas in common with one another. 
     
     
       35. The method of claim 31 wherein the second mask is formed over all of the array region. 
     
     
       36. The method of claim 31 wherein the second mask is formed over some of the periphery region. 
     
     
       37. The method of claim 31 wherein said first doping is conducted with the first mask in place. 
     
     
       38. The method of claim 31 wherein said second doping is conducted with the second mask in place. 
     
     
       39. The method of claim 31 wherein said first doping is conducted with the first mask in place, and said second doping is conducted with the second mask in place. 
     
     
       40. The method of claim 31 wherein the second mask is formed over at least a portion of the periphery region, and the second etch leaves a composite hedge of the dielectric material and the conductive material relative to an interface of the array region and the periphery region. 
     
     
       41. A method of forming a memory device on a semiconductor substrate, comprising the steps of: providing a structure on a semiconductor substrate, said structure comprising a memory array region having a plurality of memory array gate areas and a plurality of memory array storage nodes, and a periphery region comprising a plurality of periphery gate areas, said structure having a layer of a dielectric material and a layer of conductive material thereon;   forming a first mask over a first portion of said memory array region and over a first portion of said periphery region;   performing a first etch to remove unmasked portions of said conductive material layer and said dielectric layer;   with the first mask in place, first doping said substrate after said first etch with a dopant;   removing said first mask from said substrate structure;   forming a second mask over substantially all of said memory array region and some of said periphery region, said first and second mask portions have areas in common with one another in both the array region and the periphery region;   performing a second etch to remove unmasked portions of said dielectric material layer and said conductive material; and   with the second mask in place, second doping said substrate with a second dopant.   
     
     
       42. The method of claim 41 wherein the second mask is formed over at least a portion of the periphery region, and the second etch leaves a composite hedge of the dielectric material and the conductive material relative to an interface of the array region and the periphery region. 
     
     
       43. A method of forming a memory device comprising the steps of: providing a structure on a semiconductor substrate, said structure comprising a memory array region having a plurality of memory array gate areas and a plurality of memory storage nodes, and a periphery it region comprising a plurality of periphery gate areas, said structure having a layer of a dielectric material and a layer of conductive material thereon; and   removing portions of said conductive layer and of said dielectric Is layer, and doping said substrate with a first dopant to form source areas and drain areas associated with each said gate area in said memory array region, and doping said substrate with a second dopant to form source and drain areas associated with said gate areas in said periphery region; said removing and said dopings being performed with no greater than two mask steps.   
     
     
       44. The method of claim 43 wherein said removing and said dopings are performed with two mask steps. 
     
     
       45. The method of claim 43 wherein at least one of said dopings comprises out diffusing a dopant from an adjacent doped layer. 
     
     
       46. The method of claim 43 wherein the removing step comprises at least two distinct removing steps using two distinct mask steps. 
     
     
       47. The method of claim 43 wherein the removing leaves a composite hedge of the dielectric material and the conductive material relative to an interface of the array region and the periphery region. 
     
     
       48. The method of claim 43 wherein the removing step comprises first and second distinct removing steps using respective first and second distinct mask steps, one of the mask and removing steps leaving a composite hedge of the dielectric material and the conductive material relative to an interface of the array region and the periphery region. 
     
     
       49. The method of claim 43 wherein the removing step comprises first and second distinct removing steps using respective first and second distinct mask steps, the second mask and the second removing step leaving a composite hedge of the dielectric material and the conductive material relative to an interface of the array region and the periphery region. 
     
     
       50. A method of forming a memory device comprising the steps of: providing a structure on a semiconductor substrate, said structure comprising a memory array region having a plurality of memory array gate areas and a plurality of memory storage nodes, and a periphery region comprising a plurality of periphery gate areas, said structure having a layer of a dielectric material and a layer of conductive material thereon;   removing portions of said conductive layer and of said dielectric layer, and doping said substrate with a first dopant to form source areas and drain areas associated with each said gate area in said memory array region, and doping said substrate with a second dopant to form source and drain areas associated with said gate areas in said periphery region;   at least one of said dopings comprising out diffusing a dopant from an adjacent doped layer;   the removing comprising first and second distinct removing steps using respective first and second distinct mask steps, one of the mask and removing steps leaving a composite hedge of the dielectric material and the conductive material relative to an interface of the array region and the periphery region; and   said removing and said dopings being performed with two mask steps.   
     
     
       51. A method of forming a memory device on a semiconductor substrate comprising the steps of: providing a structure on said substrate, said structure comprising a memory array region having a first plurality of memory array gate areas and a plurality of memory array storage nodes, and an additional region comprising a plurality of additional gate areas, said structure having a layer of dielectric material and a layer of a conductive material formed thereon;   performing a first mask and patterning operation to remove first selected portions of said conductive layer and of said dielectric layer, and doping said substrate with said first mask in place;   removing said first mask from said structure; and   performing a second mask and patterning operation to remove second selected portions of said conductive layer and of said dielectric layer, and doping said substrate with a second dopant with said second mask in place.   
     
     
       52. The method of claim 51 wherein said first and second mask overly portions of the substrate which are common with one another. 
     
     
       53. The method of claim 51 wherein the second mask is formed over at least some of the array region. 
     
     
       54. The method of claim 51 wherein the second mask is formed over all of the array region. 
     
     
       55. The method of claim 51 wherein the second mask is formed over some of the periphery region.