Method for manufacturing diffused channel insulated gate effect transistor

Abstract

A diffused channel insulated gate field effect transistor comprised of a gate isolation layer and a gate electrode positioned on an upper surface of a semiconductor substrate of a first conductivity type; a body region of a second conductivity type present in the semiconductor substrate lying below a part of the gate electrode, on at least one side thereof, and extending downwards to a first depth; a source region of said first conductivity type present in the body region, spaced away from the first end of the gate electrode, at the upper surface and extending downwards therefrom to a second depth, shallower than the first depth; and a lightly doped region of the first conductivity type present in the body region, at least partly between the source region and the gate electrode, extending downwards to a substantially shallower depth than the second depth.

What is claimed is: 
     
       1. A method for manufacturing a diffused channel insulated gate field effect transistor, comprising the steps of: providing a semiconductor substrate of a first conductivity type, said semiconductor substrate having an upper surface;   forming a gate isolation layer and a gate electrode on said upper surface of said substrate;   implanting a first dopant of a second conductivity type at a first doping density into a region of said substrate around said gate electrode;   in the absence of thermal annealing said first dopant, implanting a second dopant of said first conductivity type at a second doping density that is less than said first doping density into said region comprising said first dopant;   in the absence of thermal annealing said second dopant, forming spacers on said upper surface of said substrate adjacent to ends of said gate electrode to cover a portion of said region comprising said second dopant;   implanting a third dopant of said first conductivity type at a third doping density that is greater than said first doping density into a portion of said region comprising said first dopant spaced away from said gate electrode by said spacers; and   performing a thermal anneal, wherein said first dopant has a diffusion rate greater than said second and third dopants during said anneal step.   
     
     
       2. The method according to claim 1, wherein said thermal anneal step is performed at a temperature of less than 1000° C. 
     
     
       3. The method according to claim 2, wherein said thermal anneal step is performed for a time duration of approximately 30 minutes. 
     
     
       4. The method according to claim 1, further comprising the step of: prior to said annealing step, implanting a fourth dopant of said second conductivity type into regions where body contacts are to be formed, wherein said implantation is performed such that, after said annealing step, said fourth dopant achieves a diffusion depth that is less than a diffusion depth achieved by said first dopant.   
     
     
       5. The method according to claim 4, wherein said first dopant is comprised of boron. 
     
     
       6. The method according to claim 5, wherein said second dopant and said third dopant are each comprised of arsenic. 
     
     
       7. The method according to claim 6, wherein said fourth dopant is comprised of boron, implanted in the form of boron fluoride. 
     
     
       8. The method according to claim 1, wherein said step of implanting said second dopant is performed in the absence of thermal annealing causes said second dopant to not substantially diffuse vertically or horizontally into said first dopant and said semiconductor substrate. 
     
     
       9. The method according to claim 1, wherein said thermal anneal step is performed for a time duration of approximately 30 minutes. 
     
     
       10. The method according to claim 1, further comprising the step of: prior to said annealing step, implanting a fourth dopant of said second conductivity type into regions where body contacts are to be formed, wherein said implantation is performed such that, after said annealing step, said fourth dopant achieves a diffusion depth that is less than a diffusion depth achieved by said first dopant.   
     
     
       11. The method according to claim 1, wherein said fourth dopant is comprised of boron, implanted in the form of boron fluoride. 
     
     
       12. The method according to claim 1, wherein said first dopant is comprised of boron. 
     
     
       13. The method according to claim 1, wherein said second dopant and said third dopant are each comprised of arsenic. 
     
     
       14. A method for manufacturing a diffused channel insulated gate field effect transistor, comprising the steps of: providing a semiconductor substrate of a first conductivity type, said semiconductor substrate having an upper surface;   forming a gate isolation layer and a gate electrode on said upper surface of said substrate;   implanting a first dopant of a second conductivity type at a first doping density into a region of said substrate adjacent to said gate electrode such that said first dopant does not substantially diffuse vertically or horizontally into said semiconductor;   implanting a second dopant of said first conductivity type at a second doping density that is less than said first doping density into said region comprising said first dopant such that said second dopant does not substantially diffuse vertically or horizontally into said semiconductor;   implanting a third dopant of said first conductivity type at a third doping density that is greater than said first doping density into said region comprising said first dopant, adjacent to a side of said second dopant opposite said gate electrode; and   performing a thermal anneal, wherein said first dopant has a diffusion rate greater than a diffusion rate of said second and third dopants during said anneal step.   
     
     
       15. The method according to claim 14, further comprising the step of: forming, prior to said third dopant implanting step, spacers on said upper surface of said substrate adjacent to ends of said gate electrode to cover a portion of said region comprising said first dopant.   
     
     
       16. The method according to claim 14, further comprising the step of: prior to said annealing step, implanting a fourth dopant of said second conductivity type into regions where body contacts are to be formed, wherein said implantation is performed such that, after said annealing step, said fourth dopant achieves a diffusion depth that is less than a diffusion depth achieved by said first dopant.   
     
     
       17. The method according to claim 14, wherein said thermal anneal step is performed at a temperature of less than 1000° C. 
     
     
       18. The method according to claim 17, wherein said thermal anneal step is performed for a time duration of approximately 30 minutes. 
     
     
       19. The method according to claim 14, further comprising the step of: implanting, prior to said annealing step, a fourth dopant of said second conductivity type into regions where body contacts are to be formed, wherein said implantation is performed such that, after said annealing step, said fourth dopant achieves a diffusion depth that is less than a diffusion depth achieved by said first dopant.   
     
     
       20. The method according to claim 14, wherein said first dopant is comprised of boron. 
     
     
       21. The method according to claim 14, wherein said second dopant and said third dopant are each comprised of arsenic. 
     
     
       22. The method according to claim 19, wherein said fourth dopant is comprised of boron, implanted in the form of boron fluoride.