Integrated circuits that include a barrier layer reducing hydrogen diffusion into a polysilicon resistor

Abstract

A barrier layer impedes hydrogen diffusion into polysilicon resistors in circuits in which the resistor resistivity is sensitive to hydrogen diffusion into the resistors. The barrier layer extends laterally throughout the whole integrated circuit except for contact areas in which circuit elements overlying the barrier layer contact conductive elements underlying the barrier layer. The barrier layer includes a layer of polysilicon or amorphous silicon. In some embodiments, the barrier layer includes multiple layers of polysilicon or amorphous silicon that are separated by thin layers of silicon dioxide. In some embodiments, the barrier layer is formed between the polysilicon resistor and PECVD silicon nitride passivation which contains atomic hydrogen.

I claim: 
     
       1. An integrated circuit comprising: a polysilicon resistor;   a barrier layer for reducing hydrogen diffusion into the polysilicon resistor, the barrier layer comprising at least two polysilicon and/or amorphous silicon layers, each layer separated from an adjacent layer by a non-silicon layer, wherein said barrier layer has a thickness of less than approximately 400 nanometers;   one or more circuit elements under the barrier layer; and   one or more circuit elements over the barrier layer which contact one or more circuit elements under the barrier layer,   wherein the barrier layer extends laterally throughout the whole integrated circuit except for one or more contact areas in which one or more circuit elements over the barrier layer contact one or more circuit elements under the barrier layer.   
     
     
       2. The integrated circuit of claim 1 wherein the non-silicon layers do not have the crystal structure of silicon. 
     
     
       3. The integrated circuit of claim 2 wherein the non-silicon layers comprise silicon oxide. 
     
     
       4. The integrated circuit of claim 1 wherein the barrier layer comprises polysilicon. 
     
     
       5. The integrated circuit of claim 1 wherein the barrier layer comprises amorphous silicon. 
     
     
       6. The integrated circuit of claim 1 further comprising a dielectric layer overlying the polysilicon resistor and underlying the barrier layer. 
     
     
       7. The integrated circuit of claim 1 wherein the barrier layer is not connected to any circuit. 
     
     
       8. The integrated circuit of claim 1 wherein the polysilicon resistor is a load resistor in a four-transistor SRAM cell. 
     
     
       9. An integrated circuit comprising a barrier layer having a plurality of polysilicon and/or amorphous silicon layers, each polysilicon and/or amorphous silicon layer separated from an adjacent polysilicon and/or amorphous silicon layer by a non-silicon layer, wherein said barrier layer has a thickness of less than approximately 400 nanometers. 
     
     
       10. The integrated circuit of claim 9, wherein the non-silicon layer comprises silicon oxide. 
     
     
       11. The integrated circuit of claim 10, wherein the silicon oxide is a thermally grown silicon oxide. 
     
     
       12. The integrated circuit of claim 9 further comprising a polysilicon resistor structure, wherein said barrier layer overlies said resistor structure. 
     
     
       13. The integrated circuit of claim 12, wherein said resistor structure is a load resistor in a four-transistor SRAM cell. 
     
     
       14. The integrated circuit of claim 12 further comprising a dielectric layer interposed between said resistor structure and said barrier layer.