Edge wrap-around protective extension for covering and protecting edges of thick oxide layer

Abstract

The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.

We claim: 
     
       1. A power transistor disposed on a substrate comprising: a core cell area comprising a plurality of power transistor cells each having drain and a source;   each of said power transistor cells further having a polycrystalline silicon gate disposed on top of said substrate;   said polycrystalline silicon gate further includes a polycrystalline silicon gate-layer-extension wherein said gate-layer extension extends as a plurality of poly-fingers away from said core cell area each having a poly-finger-end disposed at a gate-metal area next to said core cell area;   an initial oxide layer disposed in said gate-metal area under said poly-finger-end wherein said poly-fingers having a greater width and length than said initial oxide layer thus covering all edges of said initial oxide layer thereunder.   
     
     
       2. The power transistor of claim 1 further comprising: a body-dopant region containing impurities of a body dopant disposed in said substrate surrounding said poly-fingers; and   said poly-fingers having a length and width exceeding a length and width of said initial oxide layer by a distance α and α is less than a lateral diffusion length D L  of said body dopant.   
     
     
       3. The power transistor of claim 1 further comprising: a gate oxide layer thinner than said initial oxide layer said gate oxide layer disposed next to said initial oxide layer covered under said poly-fingers thus defining a thin-oxide-thick-oxide interface point between said gate-oxide layer and said initial oxide layer wherein said thin-oxide-thick-oxide interface point is covered under and protected by said poly-fingers having a greater length and width than said initial oxide layer.   
     
     
       4. A power transistor disposed on a substrate comprising: an initial oxide layer disposed on and surrounding an core cell area comprising a plurality of power transistor cells each having drain and a source on said substrate thus defining a plurality of bottom corners between a top surface of said substrate and a plurality of edge-bottoms of said initial oxide layer;   a polycrystalline silicon layer disposed on top of said initial oxide layer wherein said polycrystalline silicon layer extends over edges of said initial oxide layer thus covering and protecting all of said bottom corners.   
     
     
       5. The power transistor of claim 4 further comprising: a body-dopant region containing impurities of a body dopant disposed in said substrate surrounding said polycrystalline silicon layer; and   said polycrystalline silicon layer having a length and width exceeding edges of said initial oxide layer by a distance α and α is less than a lateral diffusion length D L  of said body dopant.   
     
     
       6. A power transistor disposed on a substrate comprising: a plurality of power transistor cells each having a drain and a source, and a gate;   a thin gate oxide layer disposed on said substrate wherein a portion thereof padded under said gate;   an initial oxide layer having a thickness greater than said gate oxide layer disposed on said substrate having at least a portion disposed adjacent to said thin gate oxide layer defining a plurality of thick-thin oxide junction points wherein said gate having a gate-extension covering all edges of said initial oxide layer and all of said thick-thin oxide junction points on said substrate.   
     
     
       7. The power transistor of claim 6 wherein: said gate comprising a polycrystalline silicon layer.   
     
     
       8. The power transistor of claim 6 wherein: said gate-extension extending beyond edges of said initial oxide layer thus covering said thick-thin junction points.   
     
     
       9. The power transistor of claim 8 further comprising: a body-dopant region containing impurities of a body dopant disposed in said substrate surrounding said gate and said gate-extension; and   said gate-extension extending beyond edges of said initial oxide layer by a distance α and α is less than a lateral diffusion length D L  of said body dopant.