Getterer for multi-layer wafers and method for making same

Abstract

A getterer structure for dielectrically isolated wafer structures such as bonded wafers. The getterer is a layer of polysilicon along the sidewalls of semiconductor regions isolated from each other by trenches. The polysilicon may be doped. The polysilicon is oxidized and polysilicon deposited to fill voids in the trenches.

I claim: 
     
       1. A wafer having a working layer and a handle layer, the working layer being divided into portions by trenches, each working layer portion having minor surfaces formed by the trenches, characterized by: a doped polysilicon gettering layer in contact with at least one of the minor surfaces providing gettering for the working layer.   
     
     
       2. The wafer as recited in claim 1, wherein the polysilicon is doped with phosphorus. 
     
     
       3. The wafer recited in claim 1, wherein the gettering layer covers substantially all of the minor surfaces. 
     
     
       4. The wafer recited in claim 3, wherein the gettering layer has a layer of oxide thereon. 
     
     
       5. The wafer recited in claim 4, wherein the trenches are filled with polysilicon. 
     
     
       6. The wafer recited in claim 5, wherein the working layer and the handle layer are separated by an insulating layer. 
     
     
       7. The wafer recited in claim 6, wherein the insulating layer is silicon dioxide. 
     
     
       8. The wafer recited in claim 7, wherein the wafer is a bonded wafer. 
     
     
       9. A dielectrically isolated wafer having a working layer and a handle layer separated by an insulating layer, the working layer being divided into portions by trenches, each working layer portion having minor surfaces formed by the trenches Characterized by: a doped polysilicon gettering layer in contact with at least one of the minor surfaces providing gettering for the working layer;   an oxide layer over the gettering layer; and   a polysilicon fill in the trenches.   
     
     
       10. The wafer recited in claim 9, wherein the polysilicon gettering layer is doped with phosphorus. 
     
     
       11. The wafer recited in claim 9, wherein the polysilicon gettering layer covers substantially all of the minor surfaces. 
     
     
       12. The wafer as recited in claim 11, wherein the insulator layer is silicon dioxide and the trench through the working layer extends to the insulating layer. 
     
     
       13. The wafer recited in claim 12, wherein the wafer is a bonded wafer. 
     
     
       14. A wafer having a silicon working layer and a handle layer, the working layer being divided into portions by trenches, each working layer portion having minor surfaces formed by the trenches, characterized by: a gettering fillet in contact with at least one of the minor surfaces providing gettering for the working layer.   
     
     
       15. The wafer recited in claim 14, wherein the gettering fillet is polysilicon. 
     
     
       16. The wafer recited in claim 15, wherein the polysilicon is doped. 
     
     
       17. The wafer recited in claim 16, wherein the polysilicon is doped with phosphorus. 
     
     
       18. The wafer recited in claims 15 or 17, wherein the gettering fillets are on substantially all of the minor surfaces. 
     
     
       19. The wafer recited in claim 18, wherein the gettering fillet has a layer of oxide thereon. 
     
     
       20. The wafer recited in claim 19, wherein the trenches are filled with polysilicon. 
     
     
       21. The wafer recited in claim 20, wherein the working layer and the handle layer are separated by an insulating layer. 
     
     
       22. The wafer recited in claim 21, wherein the insulating layer is silicon dioxide. 
     
     
       23. The wafer recited in claim 22, wherein the wafer is a bonded wafer.