Shallow trench isolation formation with deep trench cap

Abstract

A composite body includes a semiconductor substrate having an oxide layer formed thereon and a nitride layer formed over the oxide layer. First and second deep trench configurations are formed in the composite body. To form a shallow isolation trench between the first and second deep trench configurations, intrinsic polysilicon upper layers of the first and second deep trench configurations and the nitride layer are planarized. A titanium layer is formed over the planarized composite body and caused to react with the intrinsic polysilicon upper layers to form first and second titanium silicide caps over the first and second deep trench configurations. A masking layer is formed over the composite body such that an opening exposes the region between the first and second deep trench configurations. An etching step that is selective to titanium silicide is then performed with the first and second deep trench caps serving as masks. Accordingly, a shallow trench is formed in the region between the first and second trench configurations. The masking layer and the first and second deep trench caps are removed, and oxide and nitride linings are formed over the first and second deep trench configurations and over the surfaces of the shallow trench to prevent oxidation.

I claim: 
     
       1. A method of forming a shallow trench in a semiconductor substrate having first and second deep trenches each filled with at least one material, said method comprising the steps of: planarizing an exterior surface of composite body comprising said semiconductor substrate;   forming first and second metal silicide caps over the material filling said first and second deep trenches; and   forming said shallow trench between said first and second deep trenches by etching the material between said first and second deep trenches using said first and second metal silicide caps as masks to protect the material filling said first and second deep trenches from being etched during the etching.   
     
     
       2. The method according to claim 1, wherein said first and second deep trenches are filled with polysilicon, and said exterior surface of said composite body comprises top surfaces of the polysilicon filling said first and second deep trenches and a silicon nitride layer which is formed on said semiconductor substrate, and wherein said step of planarizing comprises planarizing the top surfaces of the polysilicon filling said first and second trenches and said silicon nitride layer to be substantially at the same level. 
     
     
       3. The method according to claim 2, wherein said step of forming said first and second metal silicide caps comprises forming a metal layer over the polysilicon filling said first and second deep trenches and causing said metal to react with the polysilicon filling said first and second deep trenches, thereby forming said first and second metal silicide caps only on the top of said polysilicon. 
     
     
       4. The method according to claim 3, wherein said metal comprises titanium and said first and second metal silicide caps comprise titanium silicide caps. 
     
     
       5. The method according to claim 4, wherein said semiconductor substrate comprises a silicon substrate and said step of forming said shallow trench comprises removal of unreacted titanium on the surface of said silicon nitride layer by a sulfuric peroxide solution and a reactive ion etching process which etches silicon nitride and silicon, but not titanium silicide. 
     
     
       6. The method according to claim 5, wherein said step of etching further comprises: forming a photoresist masking layer having a pattern of openings over a surface of said composite body after forming said first and second titanium silicide caps, wherein the pattern of openings includes an opening exposing a portion of said first and second titanium silicide caps and the material therebetween; and   etching the material between said first and second titanium silicide caps using said first and second titanium silicide deep trench caps and said photoresist layer as masks.   
     
     
       7. The method according to claim 6, further comprising the steps of: stripping said first and second titanium silicide caps using hydrofluoric acid; and   forming a nitride lining over an interior surface of said shallow trench.   
     
     
       8. The method according to claim 1, wherein said metal silicide caps comprise titanium silicide. 
     
     
       9. The method according to claim 1, wherein said semiconductor substrate comprises a silicon substrate and said step of forming said shallow trench comprises a reactive ion etching process for etching silicon between said first and second silicide caps to form said shallow trench between said first and second deep trenches. 
     
     
       10. A method of forming a shallow trench isolating structure for isolating first and second deep trenches formed in a semiconductor substrate, the method comprising the steps of: forming silicide caps over material filling said first and second deep trenches;   forming a shallow trench between said first and second deep trenches using an anisotropic etch for etching the material between said first and second deep trenches using said silicide caps as masks to protect the material filling said first and second deep trenches from being etched; and   filling said shallow trench with an insulating material.   
     
     
       11. A method of forming a shallow trench isolation structure, the method comprising the steps of: forming first and second deep trenches in said semiconductor substrate;   filling said first and second deep trenches with conductive material which is insulatively spaced from said semiconductor substrate;   forming a metal layer on an upper surface of the conductive material filling said first and second deep trenches;   reacting said metal layer and a portion of said conductive material filling said first and second deep trenches to form first and second metal silicide layers on the unreacted portions of said conductive material filling said first and second deep trenches, respectively;   etching the portion of said semiconductor substrate between said first and second deep trenches using said first and second metal silicide layers as a mask to form a shallow trench;   removing said first and second metal silicide layers; and   filling said shallow trench with an insulator.   
     
     
       12. The method according to claim 11, comprising the further step of: forming a liner in said shallow trench before filling said shallow trench with an insulator.   
     
     
       13. The method according to claim 11, wherein said liner comprises a nitride layer. 
     
     
       14. The method according to claim 11, wherein said liner comprises an oxide layer and a nitride layer. 
     
     
       15. A method of forming a shallow trench isolation structure in a semiconductor substrate, the method comprising the steps of: forming first and second deep trenches in said semiconductor substrate onto which a pad layer is formed;   filling said first and second deep trenches with conductive material;   planarizing upper surfaces of said pad layer and the conductive material filling said first and second deep trenches;   forming a metal layer on the planarized upper surfaces of said pad layer and the conductive material filling said first and second deep trenches;   reacting said metal layer and a portion of said conductive material filling said first and second deep trenches to form first and second metal silicide layers on the unreacted portions of said conductive material filling said first and second deep trenches, respectively;   stripping the unreacted portions of said metal layer from the upper surface of said pad layer;   forming a masking layer on upper surfaces of said pad layer and said first and second metal silicide layers;   patterning said masking layer to have an opening which at least exposes the portion of said pad layer between said first and second deep trenches;   etching said pad layer and said semiconductor substrate using said patterned masking layer and said first and second metal silicide layers as a mask to form a shallow trench;   removing said masking layer and first and second metal silicide layers; and   filling said shallow trench with an insulator.   
     
     
       16. The method according to claim 15, wherein said shallow trench has tapered sidewalls. 
     
     
       17. The method according to claim 15, comprising the further step of: forming a liner in said shallow trench before filling said shallow trench with an insulator.   
     
     
       18. The method according to claim 15, wherein said metal layer and said conductive material filling said first and second deep trenches are reacted such that a level of the unreacted portions of said conductive material filling said first and second deep trenches is lower than a level of the surface of said semiconductor substrate on which said pad layer is formed. 
     
     
       19. The method according to claim 15, wherein said masking layer comprises a photoresist. 
     
     
       20. The method according to claim 15, wherein said shallow trench is filled by an oxide which is deposited using chemical vapor deposition.