Method of manufacturing a semiconductor device

Abstract

A semiconductor device, and a method of manufacturing the same, containing a high voltage DMOS transistor, a low voltage CMOS transistor, and a bipolar transistor in a single substrate. The steps include forming an isolation layer within the substrate in an isolation region between each of a DMOS region, a CMOS region, or a bipolar region. A first oxide layer of variable thickness is formed on the substrate, a thick second oxide layer is formed on the isolation layer, and a polysilicon layer is formed on both oxide layers. The polysilicon layer is patterned to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer. The gate pattern is then doped but the resistive pattern is undoped. The thickness of the first oxide layer in the DMOS region is greater than the thickness of the first oxide layer in the CMOS region.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device containing a DMOS transistor, a CMOS transistor and a bipolar transistor in a single substrate, comprising the steps of: forming an isolation layer within the substrate in a plurality of isolation regions between each of a DMOS region, a CMOS region, and a bipolar region;   forming a discontinuous first oxide layer of variable thickness on the substrate, excluding the isolation regions;   forming a second oxide layer on the isolation layer;   depositing a polysilicon layer on the first oxide layer and on the second oxide layer;   patterning the polysilicon layer to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer; and   doping the gate patterns.   
     
     
       2. The method of claim 1, wherein the thickness of the first portion of the first oxide layer in the DMOS region is greater than the thickness of the second portion of the first oxide layer in the CMOS region. 
     
     
       3. The method of claim 1, the step of forming the first oxide layer comprising the steps of: removing portions of an extant oxide film on the surface of the substrate in the CMOS region; and   performing an oxidation process over all regions for forming the first oxide layer with a greater thickness in the DMOS region than in the CMOS region.   
     
     
       4. The method of claim 1, the step of doping comprising the steps of: depositing a third oxide layer over the gate patterns and resistive patterns;   removing a portion of the third oxide layer overlying the gate patterns;   infusing the polysilicon layer with a dopant in the gate patterns using the third oxide layer as a mask; and   removing the third oxide layer.   
     
     
       5. The method of claim 1, wherein the polysilicon layer has a thickness in the range from about 2,000 Å to about 6,000 Å. 
     
     
       6. A method of manufacturing a semiconductor having a DMOS transistor, a CMOS transistor, and a bipolar transistor in a single substrate, comprising: forming an isolation layer within the substrate in a plurality of isolation regions between each of a DMOS region, a CMOS region, and a bipolar region;   depositing a first oxide layer over the substrate;   depositing a nitrite layer over the substrate, the nitrite layer including a first portion, formed over the isolation regions, and a second portion;   removing the first portion of the nitride layer;   forming a second oxide layer for isolation over the isolation regions by oxidation;   removing the second portion of the nitride layer;   removing a portion of the first oxide layer in the CMOS region;   forming a third oxide layer over the substrate;   depositing a polysilicon layer over the third oxide layer;   patterning the polysilicon layer to form gate patterns in the CMOS region and resistive patterns in the isolation regions; and   doping the gate patterns.   
     
     
       7. The method of claim 6, wherein the polysilicon layer is an undoped layer. 
     
     
       8. The method of claim 6, wherein a step of doping the gate patterns comprises: depositing a fourth oxide layer over the gate patterns and the resistive patterns;   removing a portion of the fourth oxide layer overlaying the gate patterns;   infusing the polysilicon layer with a dopant in the gate patterns using the fourth oxide layer as an implant mask; and   removing the fourth oxide layer.   
     
     
       9. The method of claim 8, further comprising doping portions of the DMOS region, the CMOS region, and the bipolar region with an n-type dopant. 
     
     
       10. The method of claim 9, further comprising doping portions of the DMOS region, the CMOS region, the bipolar region, and the resistive pattern located in the isolation region proximate to the DMOS region with a p-type dopant.