Interleaved burst address counter with reduced delay between rising clock edge and burst address transfer to memory

Abstract

A burst address sequencer and method for providing sequential addresses to a memory which operates in response to a clock signal. The burst address sequencer includes a plurality of two-stage address registers, with an address register being provided for each address bit. Prior to an initial rising edge of the clock signal, an initial address is loaded into the first stages of the two-stage address registers. In response to the initial rising edge of the clock signal, the initial address is clocked through the second stages of the two-stage address registers, directly to the memory. Subsequent addresses are derived from the initial address by circuitry within the burst address sequencer. These subsequent burst addresses are provided to the first stages of the addresses registers prior to subsequent rising edges of the clock signal and clocked out to the memory in response to these subsequent rising edges of the clock signal. By providing the addresses directly from the second stage of the address registers to the memory, the logic gate delay associated with providing the addresses to the memory in response to the rising edge of the clock signal is minimized.

We claim: 
     
       1. A burst address sequencer for accessing a memory which operates in response to a clock signal, the burst address sequencer comprising: a first plurality of registers for storing a first plurality of address bits which are changed during a burst address sequence, wherein the first plurality of registers are directly connected to the memory;   a second plurality of registers for storing a second plurality of address bits which remain unchanged during a burst address sequence, wherein the second plurality of registers are directly connected to the memory;   a first plurality of multiplexers coupled to receive the first plurality of address bits, wherein the first plurality of multiplexers pass the first plurality of address bits, thereby causing the first plurality of address bits to be loaded into the first plurality of registers in response to a load control signal;   a second plurality of multiplexers coupled to receive the second plurality of address bits, wherein the second plurality of multiplexers pass the second plurality of address bits, thereby causing the second plurality of address bits to be loaded into the second plurality of registers in response to the load control signal; and   a clock signal line which transmits the clock signal, the clock signal line being coupled to each of the first and second plurality of registers, wherein the first and second plurality of address bits are transmitted directly from the first and second plurality of registers to the memory in response to a first transition of the clock signal.   
     
     
       2. The burst address sequencer of claim 1, wherein less than two logic gate delays are introduced in transmitting the first and second plurality of address bits from the first and second plurality of registers to the memory.