Bus driving system and integrated circuit device using the same

Abstract

A bus driving system includes n bus wires having data signal wires and control signal wires, (n-1) switching circuits constituting driver circuits at a transmitting end, a precharge circuitry for precharging (n-2) bus wires and (n-1)-th bus wire with a control circuit for redistributing wire capacitances of transmission lines formed by the bus wires, and a predischarge circuitry for predischarging n-th bus wire. The switching circuits control conduction and non-conduction between (n-2) bus wires, (n-1)-th bus wire and n-th bus wire, wherein the (n-2) switching circuits respond to (n-2) bit signals and a control signal, while the (n-1)-th switching circuit responds to the control signal. The signal from the transmitting end is detected by a detection circuit at a receiving end via the transmission lines.

What is claimed is: 
     
       1. A bus driving system, comprising: bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;   a driver circuit provided at said transmitting end for driving said bus wires;   a control circuit for redistributing wiring capacitances of transmission lines formed by said bus wires; and   a detection circuit provided at said receiving end for detecting bus signals.   
     
     
       2. A bus driving system according to claim 1, wherein said control circuit includes a charge circuit for supplying substantially a supply voltage to said driver circuit, and a discharge circuit for supplying substantially a ground level to said drive circuit.   
     
     
       3. A bus driving system according to claim 2, wherein said discharge circuit includes a switch circuit for discharging electric charge stored in wiring capacitances of said bus wires.   
     
     
       4. A bus driving system according to claim 2, wherein said charge circuit includes a switch circuit for charging electric charge stored in wiring capacitances of said bus wire.   
     
     
       5. A bus driving system according to claim 1, wherein said driver circuit includes driving MOSFET elements, conductors to which either drain paths or source paths of said driving MOSFET elements are connected in common, are wired from said transmitting end to said receiving end.   
     
     
       6. A bus driving system according to claim 5, wherein said driving MOSFET elements include a parallel connection of a p-channel MOSFET and an n-channel MOSFET.   
     
     
       7. A bus driving system according to claim 5, wherein said driving elements includes a NAND circuit and a p-channel MOSFET for driving a signal from said NAND circuit.   
     
     
       8. A bus driving system according to claim 1, further comprising:   a first control wire on which said control signal is usually at zero level and assumes an intermediate level between said substantial supply voltage and said substantial ground level upon redistribution of wiring capacitances of the transmission lines formed by said bus wires.   
     
     
       9. A bus driving system according to claim 1, further comprising:   a first control wire for carrying said control signal; and   a second control wire of which potential is usually at a supply voltage level and assumes an intermediate level between said substantial supply voltage level and said substantial ground level upon redistribution of wiring capacitances of the transmission lines formed by said wires.   
     
     
       10. A bus driving system according to claim 9, wherein said bus wires includes a plurality of sets of wires, each of said sets includes a data signal wire, said first control signal wire and said second control signal wire.   
     
     
       11. A bus driving system according to claim 1, wherein said bus wires includes a plurality of sets of wires, each of said sets includes a data signal wire, a first control wire for carrying said control signal, and a second control wire of which potential is usually at a supply voltage level and assumes an intermediate level between said substantial supply voltage level and said substantial ground level upon redistribution of wiring capacitances of the transmission lines formed by said wires.   
     
     
       12. A bus driving system according to claim 1, wherein said detection circuit includes:   a signal generating circuit for generating an activation signal, a second control signal and a reference signal of said substantial supply voltage level; and   a latch circuit for regenerating a signal level on the basis of a signal outputted from said signal generating circuit.   
     
     
       13. A bus driving system according to claim 12, further comprising a circuit for generating said activation signal which contains a signal for charging the wiring capacitances of said bus signal wires and a signal for discharging the wiring capacitances of said control wires.   
     
     
       14. A bus system, comprising: a bus driving system including: bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;   a driver circuit for driving said bus wires at said transmitting end;   a charge circuit for charging wiring capacitance of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;   control wires for redistributing wiring capacitance of said bus wires;   a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires; and   a detection circuit for detecting data signals from said bus wires at said receiving end; and     a bus interface for interconnecting execution/control means, memory means storing data signals and an external bus to one another via said bus driving system.   
     
     
       15. In an information processing system which comprises antenna means for transmitting and receiving a radio signal, a modulator/demodulator circuit for converting said signal supplied from said antenna means, at least one of a digital-to-analogue converter for converting said signal into an analogue signal and an analogue-to-digital converter for converting said signal into a digital signal, and memory means for storing information; a base band LSI (Large Scale Integrated circuit) for controlling said information processing system, comprising:   bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;   a driver circuit for driving said bus wires at said transmitting end;   a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;   control wires for redistributing wiring capacitances of said bus wires;   a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires; and   a detection circuit for detecting data signals from said bus wires at said receiving end;   arithmetic means for arithmetically determining data to be sent to said information processing system;   data address control means for controlling addresses of said data;   instruction-dedicated read-only memory means for storing instructions commanding operations of said information processing system;   program control means for controlling operations of said information processing system; and   bus interface means for connection to said information processing system.   
     
     
       16. An integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system which comprises:   bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;   a driver circuit for driving said bus wires at said transmitting end;   a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;   control wires for redistributing wiring capacitances of said bus wires;   a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires; and   a detection circuit for detecting data signals from said bus wires at said receiving end.   
     
     
       17. An integrated circuit device including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system which comprises:   bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;   a driver circuit for driving said bus wires at said transmitting end;   a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;   control wires for redistributing wiring capacitances of said bus wires;   a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires; and   a detection circuit for detecting data signals from said bus wires at said receiving end,   said integrated circuit device being implemented in the form of a package;   wherein at least a power source wire, a ground wire and said control wires are led out to corresponding pins of said package.   
     
     
       18. A bus driving system for transmitting data of n bits (where n is a positive integer), comprising: (n+2) wires including first to (n+2)-th wires;   at least one set of (n+1) switching circuits including first to (n+1)-th switching circuits;   means for making potentials at said first to (n+1)-th wires coincide with a level of a first operation potential level; and   means for making potential at said (n+2)-th wire coincide with a second operation potential level;   wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+1)) controls conduction and non-conduction between said k-th wire and said (n+2)-th wire;   said first to n-th switching circuits responding to said first to n-th bit signals, respectively; and   wherein said first to (n+1)-th switching circuits respond to a first control signal.   
     
     
       19. A bus driving system according to claim 18, wherein said k-th switching circuit (where k is greater than 1 (one) and smaller than (n+1) inclusive thereof) includes an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain-source path connected between said k-th wire and said (n+2)-th wire.   
     
     
       20. A bus driving system according to claim 18, wherein said k-th switching circuit (where k is greater than 1 (one) and smaller than (n+1) inclusive thereof) includes a p-channel MOSFET having a drain-source path connected between said k-th wire and said (n+2)-th wire.   
     
     
       21. A bus driving system according to claim 18, wherein said bus including at least one set of first to n-th amplifier circuits,   an i-th amplifier circuit (where i represents a given integer greater than 1 (one) and smaller than n inclusive thereof) includes:   first and second n-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) each having a source terminal connected to a first node and a drain terminal connected to a second node;   third and fourth n-channel MOSFETs each having a source terminal connected to said first node and a drain terminal connected to a third node;   a fifth n-channel MOSFET having a source terminal connected to said second node, a drain terminal connected to a fourth node and a gate terminal connected to a fifth node;   a sixth n-channel MOSFET having a source terminal connected to said third node, a drain terminal connected to said fifth node and a gate terminal connected to said fourth node;   a first p-channel MOSFET having a drain terminal connected to said fourth node, a gate terminal connected to said fifth node and a source terminal connected to a first power source;   a second p-channel MOSFET having a drain terminal connected to said fifth node, a gate terminal connected to said fourth node and a source terminal connected to said first power source;   a switching circuit for controlling conduction and non-conduction between said fourth node and said first power source;   a switching circuit for controlling conduction and non-conduction between said fifth node and said first power source; and   a switching circuit for controlling conduction and non-conduction between said first node and a second power source;   wherein the gate terminals of said first and second n-channel MOSFETs are connected to the i-th wire; and   wherein one of the gate terminals of said third and fourth n-channel MOSFETs is at a same potential as said first operation potential level while the other gate terminal is connected to said (n+1)-th wire.   
     
     
       22. A bus driving system according to claim 21, further comprising:   means for making said second node and said third node at a same potential level.   
     
     
       23. A bus driving system according to claim 21, further comprising:   a switching circuit for controlling conduction and non-conduction between said second node and said first power source; and   a switching circuit for controlling conduction and non-conduction between said third node and said first power source.   
     
     
       24. A bus driving system according to claim 18, further comprising:   a (n+3)-th wire (where n represents a positive integer); and   means for making potential of said (n+3)-th wire coincide with said first operation potential level.   
     
     
       25. A microprocessor including a bus driving system for driving a n-bit data bus (where n is a positive integer), said bus driving system comprising:   (n+2) wires including first to (n+2)-th wires;   at least one set of (n+1) switching circuits including first to (n+1)-th switching circuits;   means for making potentials at said first to (n+1)-th wires coincide with a level of a first operation potential level; and   means for making potential at said (n+2)-th wire coincide with a second operation potential level;   wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+1)) controls conduction and non-conduction between said k-th wire and said (n+2)-th wire;   said first to n-th switching circuits responding to said first to n-th bit signals, respectively; and   wherein said first to (n+1)-th switching circuits respond to a first control signal.   
     
     
       26. A package board including a plurality of chips mounted on a board, and a bus driving system used as an external bus for interconnection of said chips, said bus driving system comprising:   (n+2) wires including first to (n+2)-th wires;   at least one set of (n+1) switching circuits including first to (n+1)-th switching circuits;   means for making potentials at said first to (n+1)-th wires coincide with a level of a first operation potential level; and   means for making potential at said (n+2)-th wire coincide with a second operation potential level;   wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+1)) controls conduction and non-conduction between said k-th wire and said (n+2)-th wire;   said first to n-th switching circuits responding to said first to n-th bit signals, respectively; and   wherein said first to (n+1)-th switching circuits respond to a first control signal.   
     
     
       27. A large scale integrated circuit (LSI) comprising: an integrated circuit; and   a plurality of input/output ports, connected to said integrated circuit, operating in synchronism with a clock signal,   wherein one of high and low levels at each of said input/output ports remains constant independent of operation cycles, while the other of said high and low levels is changed depending on the operation cycles.   
     
     
       28. A bus driving system for driving a bus for data of n bits (where n is a positive integer), comprising: (n+1) wires including first to (n+1)-th wires;   at least one set of n switching circuits including first to n-th switching circuits;   means for making potentials at said first to n-th wires coincide with a first operation potential level; and   means for making potential at said (n+1)-th wire coincide with a second operation potential level;   wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than n) controls conduction and non-conduction between said k-th wire and said (n+1)-th wire,   said first to n-th switching circuits responding to said first to n-th bit signals and a first control signal, respectively.   
     
     
       29. A method for controlling a bus driving system, said bus being connected to a circuit, said method comprising the step of: controlling the bus driving system by keeping constant a total sum of charge stored in capacitances parasitic to wires of a bus independent of a level of input data throughout a period from a time point at which precharge of the bus is completed to a time point at which a signal makes appearance at the bus.   
     
     
       30. A bus driving system, comprising: bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;   a driver circuit provided at said transmitting end for driving said bus wires;   a control circuit for redistributing wiring capacitances of transmission lines formed by said bus wires; and   a detection circuit provided at said receiving end for detecting bus signals,   said control signals being delivered from first to fourth control wires;   wherein said first control wire is usually at zero level and assumes an intermediate level between a level substantially equal to the supply voltage level and a level substantially equal to the ground level upon redistribution of the wiring capacitances of the transmission lines formed by said bus wires;   said second and third control wires are usually at said supply voltage level and assume an intermediate level between a level substantially equal to the supply voltage level and a level substantially equal to the ground level upon redistribution of the wiring capacitances of the transmission lines formed by said bus wires, respectively; and   wherein said fourth wire is disposed adjacent to said second and third control lines and usually at said supply voltage level while assuming a level substantially equal to said supply voltage level upon redistribution of the wiring capacitances of the transmission lines formed by said bus wires.   
     
     
       31. A bus driving system according to claim 30, wherein said detection circuit includes:   a signal generation circuit for generating an activation signal and a reference voltage from the control signal delivered from either one of said second or third control line and the control signal delivered from said fourth control line; and   a latch circuit for regenerating a signal level on the basis of the signals outputted from said signal generation circuit.   
     
     
       32. A bus driving system for transmitting data of n bits (where n is a positive integer), comprising: (n+4) wires including first to (n+4)-th wires;   at least one set of (n+2) switching circuits including first to (n+2)-th switching circuits;   means for making potentials at said first to (n+3)-th wires coincide with a level of a first operation potential level; and   means for making potential at said (n+4)-th wire coincide with a second operation potential level;   wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+2)) controls conduction and non-conduction between said k-th wire and said (n+4)-th wire;   said first to n-th switching circuits responding to said first to n-th bit signals, respectively; and   wherein said first to (n+2)-th switching circuits respond to a first control signal.   
     
     
       33. A bus driving system according to claim 32, wherein said k-th switching circuit includes a n-channel MOSFET having a drain-source path connected between said k-th wire and said (n+4)-th wire.   
     
     
       34. A bus driving system according to claim 32, wherein said k-th switching circuit includes a p-channel MOSFET having a drain-source path connected between said k-th wire and said (n+4)-th wire.   
     
     
       35. A bus driving system according to claim 32, wherein said (n+3)-th wire is disposed adjacent to said (n+1)-th wire and said (n+2)-th wire.   
     
     
       36. A bus driving system according to claim 32, wherein said bus including at least one set of first to n-th amplifier circuits,   an i-th amplifier circuit (where i represents a given integer greater than 1 (one) and smaller than n inclusive thereof) includes:   first and second n-channel MOSFETs each having a source terminal connected to a first node and a drain terminal connected to a second node;   third and fourth n-channel MOSFETs each having a source terminal connected to said first node and a drain terminal connected to a third node;   a fifth n-channel MOSFET having a source terminal connected to said second node, a drain terminal connected to a fourth node and a gate terminal connected to a fifth node;   a sixth n-channel MOSFET having a source terminal connected to said third node, a drain terminal connected to said fifth node and a gate terminal connected to said fourth node;   a first p-channel MOSFET having a drain terminal connected to said fourth node, a gate terminal connected to said fifth node and a source terminal connected to a first power source;   a second p-channel MOSFET having a drain terminal connected to said fifth node, a gate terminal connected to said fourth node and a source terminal connected to said first power source;   a switching circuit for controlling conduction and non-conduction between said fourth node and said first power source;   a switching circuit for controlling conduction and non-conduction between said fifth node and said first power source; and   a switching circuit for controlling conduction and non-conduction between said first node and a second power source;   wherein the gate terminals of said first and second n-channel MOSFETs are connected to the i-th wire; and   wherein one of the gate terminals of said third and fourth n-channel MOSFETs is connected to said (n+1)-th wire while the other gate terminal is connected to said (n+2)-th wire.   
     
     
       37. A driver circuit including a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire, and an n-channel MOS transistor having a source-drain path connected between said output wire and a circuit point of a second operation potential level, wherein gates of said p-channel MOS transistor and said n-channel MOS transistor responds to a data input signal, whereby an output signal relevant to said data input signal is delivered onto said output wire, said driver circuit further comprising:   a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level; and   a control circuit controlled by a precharge signal, an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;   wherein the gate of said n-channel MOS switching transistor is controlled by said precharge control signal.   
     
     
       38. A semiconductor integrated circuit which comprises a chip incorporating therein a CPU, a memory, a peripheral circuit and an internal bus, and a driver circuit disposed between said internal bus and at least one of said CPU and said peripheral circuit, said driver circuit including:   a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire;   an n-channel MOS transistor having a source-drain path connected between said output wire, and a circuit point of a second operation potential level;   gates of said p-channel MOS transistor and said n-channel MOS transistor responding to a data input signal, to thereby deliver an output signal relevant to said data input signal onto said output wire;   a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level; and   a control circuit controlled by a precharge signal, an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;   wherein the gate of said n-channel MOS switching transistor is controlled by said precharge control signal.   
     
     
       39. A semiconductor integrated circuit according to claim 38, wherein said chip constitutes an application specific integrated circuit (ASIC) incorporating either a single-chip microcomputer or a CPU core.   
     
     
       40. A driver circuit including a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire, and an n-channel MOS transistor having a source-drain path connected between said output wire and a circuit point of a second operation potential level, wherein gates of said p-channel MOS transistor and said n-channel MOS transistor responds to a data input signal, whereby an output signal relevant to said data input signal is delivered onto said output wire, said driver circuit further comprising:   a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level; and   a control circuit controlled by an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;   wherein the gate of said n-channel MOS switching transistor is driven by a signal of a phase opposite to that of the signal driving the gate of said n-channel MOS transistor.   
     
     
       41. A semiconductor integrated circuit which comprises a chip incorporating therein a CPU, a memory, a peripheral circuit and an internal bus, and a driver circuit disposed between said internal bus and at least one of said CPU and said peripheral circuit, said driver circuit including:   a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire;   an n-channel MOS transistor having a source-drain path connected between said output wire, and a circuit point of a second operation potential level;   gates of said p-channel MOS transistor and said n-channel MOS transistor responding to a data input signal, to thereby deliver an output signal relevant to said data input signal onto said output wire;   a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level; and   a control circuit controlled by an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;   wherein the gate of said n-channel MOS switching transistor is driven by a signal of a phase opposite to that of the signal driving the gate of said n-channel MOS transistor.   
     
     
       42. A semiconductor integrated circuit according to claim 41, wherein said chip constitutes an application specific integrated circuit (ASIC) incorporating either a single-chip microcomputer or a CPU core.   
     
     
       43. An information processing system comprising: antenna means for transmitting and receiving a radio signal;   a modulator/demodulator circuit for converting said signal supplied from said antenna means;   a digital-to-analog converter for converting said signal into an analog signal;   an analog-to-digital converter for converting said signal into a digital signal;   a memory means for storing information; and   an integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system comprising: bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals,   a driver circuit provided at said transmitting end for driving said bus wires,   a control circuit for redistributing wiring capacitances of transmission lines formed by said bus wires, and   a detection circuit provided at said receiving end for detecting bus signals.     
     
     
       44. An integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system comprising: bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;   a driver circuit provided at said transmitting end for driving said bus wires;   a control circuit for redistributing wiring capacitances of transmission lines formed by said bus wires; and   a detection circuit provided at said receiving end for detecting bus signals.   
     
     
       45. An information processing system comprising: antenna means for transmitting and receiving a radio signal;   a modulator/demodulator circuit for converting said signal supplied from said antenna means;   a digital-to-analog converter for converting said signal into an analog signal;   an analog-to-digital converter for converting said signal into a digital signal;   a memory means for storing information; and   an integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system comprising: bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals,   a driver circuit for driving said bus wires at said transmitted end,   a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end,   control wires for redistributing wiring capacitances of said bus wires,   a switch circuit for discharging an electric charge stored in said wiring capacitances of said control wires, and   a detection circuit for detecting data signals from said bus wires at said receiving end.