Ultra-shallow semiconductor junction formation

Abstract

A method for fabricating an ultra-shallow semi-conductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

Having thus described my invention, what I claim as new, and desire to secure by Letters Patent is: 
     
       1. A structure having an abrupt p-n junction, said structure comprising a shallow implant region defined by dopant material of a first conductivity type formed in a surface of a semiconductor substrate of a second conductivity type, said substrate comprising a region of coalesced high concentrations of interstitial ions of said semiconductor substrate disposed substantially at a first depth, said shallow implant region having a second depth less than said first depth wherein the concentration of said dopant material at a boundary junction of said shallow implant region changes by a factor of 10 within a distance of less than 60 Å measured at, and perpendicular to, said boundary. 
     
     
       2. The structure of in claim 1, wherein said second depth is less than 500 Å. 
     
     
       3. The structure of claim 1, wherein the change of concentration of said dopant material at the boundary junction is measured at a dopant concentration of 1×10 18  /cm 2 . 
     
     
       4. The structure of claim 1, wherein said first depth is about 10,000 Å. 
     
     
       5. A field effect transistor comprising a microelectronic device comprising a source region and a drain region formed in mutually spaced adjacency in a surface of a semiconductor substrate, a pair of said shallow implant regions being disposed between and formed as spaced-apart extensions of said source and drain regions to form a channel region between the spaced-apart shallow implant regions, and a gate electrode overlying said channel region, wherein said semiconductor substrate contains regions of coalesced high concentrations of interstitial ions of said semiconductor substrate disposed substantially at a first depth and said shallow implant region having a second depth less than said first depth wherein the concentration of said dopant material at a boundary junction of said shallow implant region changes by a factor of 10 within a distance of less than 60 Å measured at, and perpendicular to, said boundary. 
     
     
       6. The field effect transistor of claim 5, wherein the distance between said spaced-apart shallow implant regions is less than about 2500 Å. 
     
     
       7. The field effect transistor of claim 5, wherein said second depth is less than 500 Å. 
     
     
       8. The field effect transistor of claim 5, wherein the change of concentration of said dopant material at the boundary junction is measured at a dopant concentration of 1×10 18  /cm 2 . 
     
     
       9. The field effect transistor of claim 5, wherein said first depth is about 10,000 Å.