Method of fabricating high density flat cell mask ROM

Abstract

A method of fabricating high-density flat cell mask ROM is disclosed. The method comprises, formed a plurality of trenches in a silicon substrate firstly. An oxynitride layer is then grown on resultant surfaces to about 1-5 nm, After refilling a plurality of trenches with a first in-situ phosphorus doping polysilicon layer or amorphous silicon, etching back the polysilicon layer to form a flat surface by a CMP process is achieved. Subsequently, a thermal oxidation process is carried out to grow an oxide layer and to form a plurality of buried bit lines by diffusing the conductive impurities in the polysilicon layer through the oxynitride layer into the silicon substrate. A second in-situ n+ doped polysilicon layer is deposited and patterned as word lines; then a patterned photoresist coated on the second polysilicon layer except predetermining coding regions. Finally, a coding boron implant into the predetermined coding region is done to form normally off transistors.

What is claimed is: 
     
       1. A method of fabricating flat cell mask ROM on a silicon substrate comprising the steps of: forming a plurality of trenches in said silicon substrate;   forming an oxynitride layer on resultant surfaces of said silicon substrate;   forming a first silicon layer with first conductivity type impurities doping to refill said a plurality of trenches;   etching back said silicon layer to form a flat surface using said oxynitride as an etching stopping layer;   performing thermal oxidation process to grow an oxide layer on said flat surface and to form a plurality of buried bit lines by diffusing said conductive impurities in said polysilicon layer through the oxynitride layer into said silicon substrate; and   forming a second silicon layer on said oxide layer with first conductivity type impurities doping to form word lines.   
     
     
       2. The method of claim 1 and further comprising the steps of: coating a photoresist on said second silicon layer to define predetermining coding regions; and   implanting said predetermined coding region by second conductivity type impurities opposite said first conductivity type impurities.   
     
     
       3. The method of claim 1, wherein said step of forming a plurality of trenches further comprises the steps of: forming a pad oxide layer on said silicon substrate;   forming a nitride layer on said pad oxide;   patterning said nitride layer;   forming spacers on sidewalls of said patterned nitride layer;   removing said patterned nitride layer;   etching back all remnant said pad oxide layers; and   etching said silicon substrate so as to form a plurality of trenches in said silicon substrate using said insulating layer as a hard mask.   
     
     
       4. The method of claim 3, wherein said nitride layer is deposited to a thickness of about 100-500 nm at a temperature about 300-800° C. by a method selected from a group comprising LPCVD and PECVD. 
     
     
       5. The method of claim 3, wherein said step of patterning said nitride layer comprises the steps of forming a photoresist pattern via lithography technology on said nitride layer and etching portions of said nitride layer which is not masked by said photoresist pattern. 
     
     
       6. The method of claim 3, wherein said step of forming spacers comprises the steps of forming an insulating layer on all surfaces and performing an anisotropic etching said insulating layer. 
     
     
       7. The method of claim 6, wherein said insulating layer is an oxide layer. 
     
     
       8. The method of claim 3, wherein said step of removing patterned nitride layer is achieved by hot H 3  PO 4  solution, said step of etching back all remnant said pad oxide layers is done by a method selected from the group consisting of dilute HF and BOE. 
     
     
       9. The method of claim 3, wherein said step of etching said silicon substrate is carried out to a depth of about 50-500 nm by a plasma etching method using bromine-based chemistries consisting of CF 3  Br and HBr/NF 3 . 
     
     
       10. The method of claim 1, wherein said oxynitride layer is formed to a thickness of about 1-5 nm at a temperature about 750-1150° C. in an ambient selected from the group comprising N 2  O and NO. 
     
     
       11. The method of claim 1, wherein said first conductivity type impurities is selected from the group consisting of arsenic containing dopants and phosphorus containing dopants. 
     
     
       12. The method of claim 1, wherein said step of performing thermal oxidation process to grow an oxide layer on said flat surface is implementedt a temperature about 750-1100° C. to thickness of 15-50 nm and 5-15 nm on said surface of first silicon layer and said silicon substrate, respectively. 
     
     
       13. The method of claim 1, wherein said step of forming a flat surface is done by a method comprising a CMP process. 
     
     
       14. The method of claim 2, wherein said step of implanting said predetermined coding region by second conductivity type impurities, said second conductivity type impurities is boron ions with an energy of about 80-300 keV and a dosage of about 5×10 11  -5×10 14  /cm 2 . 
     
     
       15. A method of fabricating flat cell mask ROM on a silicon substrate comprising the steps of forming a pad oxide layer on said silicon substrate;   forming a nitride layer on said pad oxide;   patterning said nitride layer;   forming an insulating layer on all surfaces of said silicon substrate;   performing an anisotropic etching said insulating layer to form spacers on sidewalls of said patterned nitride layer;   removing said patterned nitride layer;   etching back all remnant said pad oxide layers;   etching said silicon substrate so as to form a plurality of trenches in said silicon substrate using said insulating layer as a hard mask;   removing all said spaces;   forming an oxynitride layer on all surfaces;   forming a first silicon layer with conductive impurities to refill said a plurality of trenches;   etching back said polysilicon layer;   performing thermal oxidation process to grow an oxide layer on said flat surface and to form a plurality of buried bit lines by diffusing said conductive impurities in said polysilicon layer through the oxynitride layer into said silicon substrate;   forming a second silicon layer with conductive impurities on said oxide layer;   patterning said second polysilicon layer to form word lines;   coating a photoresist on said second silicon layer to define a predetermining coding region, said predetermining coding region; and   implanting said predetermined coding region.   
     
     
       16. The method of claim 15, wherein said nitride layer is deposited to a thickness of about 100-500 nm at a temperature about 400-800° C. by a method selected from the group comprising of LPCVD and PECVD. 
     
     
       17. The method of claim 15, wherein said step of etching said silicon substrate is carried out to a depth of about 50-500 nm which is measured from the upper surface of said silicon substrate to the bottom of trench by a dry etching method. 
     
     
       18. The method of claim 15, wherein said first conductivity type impurities is selected from the group consisting of arsenic containing dopants and phosphorus containing dopants. 
     
     
       19. The method of claim 15, wherein said step of performing thermal oxidation process to grow an oxide layer on said flat surface is implement at a temperature about 750-1100° C. to thickness of 15-50 nm and 5-15 nm on said surface of first silicon layer and said silicon substrate, respectively. 
     
     
       20. The method of claim 15, wherein said step of implanting said predetermined coding region by second conductivity type impurities, said second conductivity type impurities is boron ions with an energy of about 80-300 keV and a dosage of about 5×10 11  -5×10 14  /cm 2 . 
     
     
       21. The method of claim 15, wherein said oxynitride layer is formed to a thickness of about 1-5 nm at a temperature about 750-1150° C. in an ambient selected from the group comprising N 2  O and NO. 
     
     
       22. The method of claim 15, wherein said second silicon layer comprises a polysilicon layer.