Delay circuit

Abstract

A delay circuit which is capable of maintaining a constant delay time. The circuit includes a plurality of first delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor connected to an output terminal of the inverter.

What is claimed is: 
     
       1. A circuit, comprising: a plurality of delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor for coupling to a ground potential and connected to an output terminal of the inverter, wherein the variable capacitor includes a transistor having a substrate for coupling to an adjustable voltage to modulate a capacitive value of the variable capacitor.   
     
     
       2. The circuit of claim 1, wherein the inverter comprises a PMOS transistor a source of which is connected with a first power voltage, and an NMOS transistor a drain of which is commonly connected with the PMOS transistor, thus forming an output terminal, and a source of which is connected with a second power voltage, the PMOS transistor and the NMOS transistor having gates commonly connected to form an input terminal. 
     
     
       3. The circuit of claim 2, wherein a substrate of said PMOS transistor is connected with a source of the PMOS transistor. 
     
     
       4. The circuit of claim 2, wherein the NMOS transistor includes a substrate having an electric potential different from that of the source of the NMOS transistor. 
     
     
       5. The circuit of claim 2, wherein said first and second power voltage are an externally applied voltage and a ground voltage, respectively. 
     
     
       6. The circuit of claim 5, wherein a substrate of said NMOS transistor has an electric potential different from that of the source of the NMOS transistor. 
     
     
       7. The circuit of claim 1, wherein said circuit is formed on a semiconductor substrate having a triple well structure. 
     
     
       8. The circuit of claim 1, further comprises a first potential coupled to each of the plurality of inverters, wherein the variable capacitor prevents a delay time that varies according to the first potential. 
     
     
       9. The circuit of claim 8, wherein the transistor of the variable capacitor includes a gate used as a first electrode, and a source and drain of which are commonly connected, thus forming a second electrode. 
     
     
       10. The circuit of claim 9, wherein the transistor is an NMOS transistor. 
     
     
       11. The circuit of claim 9, wherein each of the inverters includes a first inverter transistor having first and second electrodes and a control electrode, the first electrode for coupling to a first voltage potential,   a second inverter transistor having first and second electrodes, and   a control electrode, the first electrode of the second inverter transistor being coupled to the second electrode of the first inverter transistor to form an output terminal, the second electrode of the second inverter transistor for coupling to a second voltage potential, and the control electrode of the second inverter transistor being coupled to the control electrode of the first inverter transistor to form an input terminal.   
     
     
       12. A delay circuit, comprising: a plurality of inverters coupled in series; and   a variable capacitor including a variable transistor having a first electrode coupled to an output of one of the inverters,   a source and drain commonly connected to form a second electrode for coupling to a ground potential, and   a substrate for coupling to a variable voltage to modulate a capacitive value of the variable capacitor.     
     
     
       13. The delay circuit of claim 12, wherein each of the inverters includes a first inverter transistor having first and second electrodes and a control electrode, the first electrode for coupling to a first voltage potential,   a second inverter transistor having first and second electrodes, and   a control electrode, the first electrode of the second inverter transistor being coupled to the second electrode of the first inverter transistor to form an output terminal, the second electrode of the second inverter transistor for coupling to a second voltage potential, and the control electrode of the second inverter transistor being coupled to the control electrode of the first inverter transistor to form an input terminal.   
     
     
       14. The delay circuit of claim 13, wherein a substrate of the first inverter transistor is coupled to the first electrode of the first inverter transistor for coupling to the first voltage potential. 
     
     
       15. The delay circuit of claim 13, wherein a substrate of the second inverter transistor is coupled to a third voltage potential different than the second voltage potential. 
     
     
       16. The delay circuit of claim 13, wherein the first and second potentials are an externally applied voltage and a ground voltage, respectively. 
     
     
       17. A delay circuit, comprising: series means for coupling a plurality of inverters in series, each inverter for coupling to a first potential; and   means for preventing a delay time that varies according to the first potential, the means for preventing including, a transistor having a gate electrode, a source electrode, a drain electrode and a substrate,   means for coupling the gate electrode to an output of one of the inverters,   means for commonly connecting the source electrode and the drain electrode for coupling to a second potential, and   means for modulating a capacitive value of the means for preventing by coupling a variable voltage to the substrate.     
     
     
       18. The delay circuit of claim 17, wherein each inverter includes: a first transistor having first and second electrodes, and a control electrode,   means for coupling the first electrode to the first potential,   a second transistor having first and second electrodes and a control electrode,   means for coupling the first electrode of the second transistor to the second electrode of the first transistor to form an output terminal,   means for coupling the second electrode of the second transistor to the second potential, and   means for forming an input terminal by coupling the control electrode of the first transistor to the control electrode of the second transistor.   
     
     
       19. The delay circuit of claim 18, further comprising: means for coupling the first electrode of the first transistor with a substrate of the first transistor; and   means for coupling a substrate of the second transistor to a third potential different than the second potential.   
     
     
       20. The delay circuit of claim 17, wherein the first and second potential are an externally applied voltage and a ground voltage, respectively.