Method for a self-aligned select gate for a split-gate flash memory structure

Abstract

A process for making a self-aligned select gate for a split-gate flash memory structure uses a patterned nitride layer and a photoresist layer to serve as masks to define a select gate length, facilitates a self-aligned ion implantation to form a drain region of a memory cell, and defines a distance between the select gate and the drain region.

What is claimed is: 
     
       1. A method for fabricating a non-volatile memory semiconductor device, comprising: forming an insulating layer over a semiconductor substrate of a first conductivity type;   forming a first polysilicon layer over the insulating layer;   forming a nitride layer over the first polysilicon layer such that first and second portions of the first polysilicon layer are exposed;   forming first and second insulating regions on the first and second exposed portions, respectively, of the first polysilicon layer;   removing the first insulating region and the first portion of the first polysilicon layer such that a first portion of the insulating layer below the first portion of the first polysilicon layer is exposed;   forming an impurity region of a second conductivity type in the semiconductor substrate below the first portion of the insulating layer;   removing the nitride layer; and   etching the first polysilicon layer such that only the second portion of the first polysilicon layer below the second insulating region remains.   
     
     
       2. The method according to claim 1, further comprising: forming a sidewall insulating layer on sidewalls of the second portion of the first polysilicon layer; and   forming a second polysilicon layer over the insulating layer, the sidewall insulating layers, and the second insulating region.   
     
     
       3. The method according to claim 2, further comprising: etching the second polysilicon layer such that a remaining portion of the second polysilicon layer overlies a portion of the impurity region and a portion of the second insulating region.   
     
     
       4. The method according to claim 3, wherein the impurity region is a first impurity region, said method further comprising: forming a second impurity region of the second conductivity type in the semiconductor substrate on a side of the second portion of the first polysilicon layer remote from the first impurity region.   
     
     
       5. The method according to claim 4, wherein forming the second impurity region includes diffusing the second impurity region in the substrate so that the second portion of the first polysilicon layer overlies a portion of the second impurity region. 
     
     
       6. The method according to claim 2, wherein forming a sidewall insulating layer includes forming an oxide layer. 
     
     
       7. The method according to claim 2, wherein forming a sidewall insulating layer includes forming a composite layer of oxide/nitride. 
     
     
       8. The method according to claim 2, wherein forming a sidewall insulating layer includes forming a composite layer of oxide/nitride/oxide.