Method for manufacturing semiconductor device using spin on glass layer

Abstract

In a method for manufacturing a semiconductor device, a dummy pattern layer is formed on a layer which is located below an insulating layer on which a spin on glass (SOG) layer is formed. The insulating layer is flattened by etching back the SOG layer. Then, a contact hole is perforated in the insulating layer, the dummy pattern layer and the layer, and a conductive layer is buried in the contact hole.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor substrate;   a dummy pattern layer formed directly on top of said semiconductor substrate;   at least one first insulating layer on top of said first dummy pattern layer and said semiconductor substrate, said first insulating layer being flattened by using a spin on glass (SOG) coating and etching process;   at least one second layer on said first insulating layer; and   a conductive layer buried in a contact hole perforated in said second and first insulating layers and said dummy pattern layer.   
     
     
       2. The device as set forth in claim 1, wherein said dummy pattern layer is made of insulating material. 
     
     
       3. The device as set forth in claim 1, wherein said dummy pattern layer is made of conductive material. 
     
     
       4. A semiconductor device comprising: a semiconductor substrate;   at least one first insulating layer formed on said semiconductor substrate;   a dummy pattern layer formed on top of said first insulating layer;   at least one second insulating layer on top of said first dummy pattern layer and said first insulating layer, said second insulating layer being flattened by using a spin on glass (SOG) coating and etching process;   at least one third insulating layer on said second insulating layer; and   a conductive layer buried in a contact hole perforated in said third, second and first insulating layers and said dummy pattern layer.   
     
     
       5. The device as set forth in claim 4, wherein said dummy pattern layer is made of insulating material. 
     
     
       6. The device as set forth in claim 4, wherein said dummy pattern layer is made of conductive material. 
     
     
       7. A semiconductor device comprising: a semiconductor substrate;   a gate electrode formed over said semiconductor substrate;   an etching stopper formed on said gate electrode;   a dummy pattern layer formed on said semiconductor substrate;   at least one first insulating layer formed on said etching layer and said dummy pattern layer;   a capacitor lower electrode layer buried in a contact hole perforated in said first insulating layer;   a capacitor insulating layer formed on said capacitor lower electrode layer;   a capacitor upper electrode layer formed on said capacitor insulating layer;   at least one second insulating layer formed on said capacitor upper electrode layer and said first insulating layer, said second insulating layer being flattened by using a spin on glass (SOG) coating and etching process;   at least one third insulating layer formed on said second insulating layer; and   a conductive layer buried in a contact hole perforated in said third, second and first insulating layers and said dummy pattern layer.   
     
     
       8. The device as set forth in claim 7, wherein said dummy pattern layer is made of the same material as said etching stopper. 
     
     
       9. A semiconductor device comprising: a semiconductor substrate;   at least one first insulating layer formed on said semiconductor substrate;   a capacitor lower electrode layer buried in a contact hole perforated in said first insulating layer;   a capacitor insulating layer formed on said capacitor lower electrode layer;   a capacitor upper electrode layer formed on said capacitor insulating layer;   a dummy pattern layer formed on said first insulating layer;   at least one second insulating layer formed on said capacitor upper electrode layer, said dummy pattern layer and said first insulating layer, said second insulating layer being flattened by using a spin on glass (SOG) coating and etching process;   at least one third insulating layer formed on said second insulating layer; and   a conductive layer buried in a contact hole perforated in said third, second and first insulating layers and said dummy pattern layer.   
     
     
       10. The device as set forth in claim 9, wherein said dummy pattern layer is made of the same material as said capacitor insulating layer and said capacitor upper electrode layer.