Method of manufacturing a CMOS Transistor

Abstract

The method of manufacturing a CMOS transistor according to the present invention comprises the steps of forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors; forming a P-well region and a N-well region in the first and second regions, respectively; forming a gate oxide film and a gate electrode on selected regions of the first and second regions; implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within the first and second regions; forming spacers at said side walls of the gate electrode and the gate oxide film; forming a high concentration implantation region in the first and second regions; and implanting N-type impurity ions into the second region to form a punch stop doping layer below said low concentration impurity implantation region of the second region.

What is claimed is: 
     
       1. A method of manufacturing a CMOS transistor, comprising the steps of: forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors;   forming a P-well region and a N-well region in said first and second regions, respectively;   forming a gate oxide film and a gate electrode on selected regions of said first and second regions;   implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within said first and second regions;   forming spacers at the side walls of said gate electrode and the gate oxide film;   forming a high concentration implantation region in said first and second regions; and   implanting N-type impurity ions into said second region to form a punch stop doping layer below said low concentration impurity implantation region of said second region.   
     
     
       2. The method of manufacturing a CMOS transistor as claimed in claim 1, wherein said low concentration impurity implantation region is formed by implanting either phosphorous (P) ion or arsenic (As) ion. 
     
     
       3. The method of manufacturing a CMOS transistor as claimed in claim 2, wherein said phosphorous ion is implanted at a dose of 1.0E12-5E14 ions/cm2 with an energy of less than 20 KeV. 
     
     
       4. The method of manufacturing a CMOS transistor as claimed in claim 2, wherein said an arsenic ion is implanted at a dose of 1.0E12-5E14 ions/cm2 with an energy of less than 50KeV. 
     
     
       5. The method of manufacturing a CMOS transistor as claimed in claim 1, wherein said punch stop doping layer is formed by implanting either phosphorous (P) ion or arsenic (As) ion at a at an angle of 30-80°. 
     
     
       6. The method of manufacturing a CMOS transistor as claimed in claim 5, wherein said phosphorous ion is implanted at a dose of 1.0E12-5E13 ions/cm2 with an energy of 5 through 30 KeV. 
     
     
       7. The method of manufacturing a CMOS transistor as claimed in claim 5, wherein said arsenic ion is implanted at a dose of 1.0E12-5E-5E13 ions/cm2 with an energy of 10 through 100KeV.