Semiconductor memory device

Abstract

A plurality of bit line pairs are provided in a semiconductor memory device. A plurality of memory cells are connected to the first bit line pairs. Also, in the semiconductor memory device, there are provided a first sense amplifier, a second bit line pair and a second sense amplifier. The first sense amplifier reads and amplifies a potential difference between the first bit line pair. A signal output from the first sense amplifier is transmitted to the second bit line pair. The second sense amplifier amplifies a potential difference between the second bit line pair. A precharge circuit is built in the second sense amplifier. The first bit line pairs are precharged by the precharge circuit.

What is claimed is: 
     
       1. A semiconductor memory device, comprises: a plurality of first bit line pairs;   a plurality of memory cells connected to said first bit line pairs;   a first sense amplifier which reads and amplifies a potential difference between said first bit line pair;   a second bit line pair to which a signal output from said first sense amplifier is transmitted;   a second sense amplifier which amplifies a potential difference between said second bit line pair; and   a precharge circuit built in said second sense amplifier, said precharge circuit conducting precharge of said first bit line pairs.   
     
     
       2. The semiconductor memory device according to claim 1, wherein said first sense amplifier has an open bit line structure. 
     
     
       3. The semiconductor memory device according to claim 1, wherein said first sense amplifier has a fall-dead bit line structure. 
     
     
       4. The semiconductor memory device according to claim 1, wherein said precharge circuit comprises: a precharge potential signal line to which a potential for precharge is transmitted during said precharge, said potential for precharge being applied to said first bit line pairs;   first and second MOS transistors having source-drain connected to said precharge potential signal line, said first and second MOS transistors being connected in series between said second bit line pair;   a precharge control signal line which is connected to gates of said first and second MOS transistors, a precharge control signal for controlling said precharge being transmitted to said precharge control signal line; and   a third MOS transistor whose gate is connected to said precharge control signal line, and whose both of source-drains are connected to said second bit line pair.   
     
     
       5. The semiconductor memory device according to claim 2, wherein the precharge circuit comprises: a precharge potential signal line to which a potential for precharge is transmitted during said precharge, said potential for precharge being applied to said first bit line pairs;   first and second MOS transistors having source-drain connected to said precharge potential signal line, said first and second MOS transistors being connected in series between said second bit line pair;   a precharge control signal line which is connected to gates of said first and second MOS transistors, a precharge control signal for controlling said precharge being transmitted to said precharge control signal line; and   a third MOS transistor whose gate is connected to said precharge control signal line, and whose both of source-drains are connected to said second bit line pair.   
     
     
       6. The semiconductor memory device according to claim 3, wherein the precharge circuit comprises: a precharge potential signal line to which a potential for precharge is transmitted during said precharge, said potential for precharge being applied to said first bit line pairs;   first and second MOS transistors having source-drain connected to said precharge potential signal line, said first and second MOS transistors being connected in series between said second bit line pair;   a precharge control signal line which is connected to gates of said first and second MOS transistors, a precharge control signal for controlling said precharge being transmitted to said precharge control signal line; and   a third MOS transistor whose gate is connected to said precharge control signal line, and whose both of source-drains are connected to said second bit line pair.   
     
     
       7. The semiconductor memory device according to claim 1, which is used for a dynamic random access memory. 
     
     
       8. The semiconductor memory device according to claim 1, wherein said first sense amplifier has a switching element which controls conduction and non-conduction between said first bit line pair.