Data processor

Abstract

A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

What is claimed is: 
     
       1. A data processor for processing instructions including a subroutine call instruction and a subroutine return instruction, each instruction being processed in a pipeline, comprising: an instruction buffer to which the instructions to be processed in the pipeline is applied, for storing the instructions;   an address generating unit for generating a subroutine return address in accordance wit the subroutine call instruction output from said instruction buffer, said generated subroutine return address being transferred to a prescribed storage location;   a program counter stack for storing said subroutine return address generated by said address generating unit, said program counter stack outputting a value stored therein as a predicted return address in a first period in accordance with the subroutine return instruction stored in said instruction buffer wherein said instruction buffer receives an instruction designated by the predicted return address output from said program counter stack, and   a judging circuit coupled to program counter stack, for judging whether the predicted return address is the same as the subroutine return address stored in the prescribed storage location in a second period in accordance with the subroutine return instruction, the first period predecing the second period, wherein   a pipeline processing of the instruction designated by the predicted return address is cancelled in response to a judging result output from said judging circuit, and an instruction designated by the subroutine return address stored in the prescribed storage location is processed in the pipeline, when the judging result indicates that the predicted return address in not the same as the subroutine return address.