US6165840AExpiredUtility

Method for fabricating a DRAM cell capacitor including forming first multilayer insulator, forming conductive plug, forming second insulator, and etching second and first insulators to form the storage node

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Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Apr 29, 1998Filed: Apr 27, 1999Granted: Dec 26, 2000
Est. expiryApr 29, 2018(expired)· nominal 20-yr term from priority
Inventors:Chang-Won ChoiChang Hwan LeeChul-Min JungMin Seok Han
H10W 20/0698H10D 1/711H10D 1/692H10B 12/00H10B 12/033
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PatentIndex Score
13
Cited by
5
References
11
Claims

Abstract

Disclosed is an improved method for fabricating a DRAM cell capacitor which can prevent over-etching of polysilicon storage node. The method includes the steps of etching a first insulating layer on a semiconductor substrate to form a storage contact hole, filling the storage contact hole with a first conductive material to form a storage contact plug, forming a second insulating layer over the first insulating layer including the storage contact plug, forming a mask over the second insulating layer to define a storage node region, using the mask and etching the second and first insulating layers to form an opening therein to an upper surface of the storage contact plug, and filling the opening with a second conductive material to form a storage node.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for fabricating a DRAM cell capacitor comprising the steps of: etching a first insulating layer on a semiconductor substrate to form a storage contact hole;   filling said storage contact hole with a first conductive material to form a storage contact plug;   forming a second insulating layer over said first insulating layer including said storage contact plug;   forming a mask over said second insulating layer to define a storage node region;   using said mask and etching said second and first insulating layers to form an opening therein to an upper surface of said storage contact plug; and   filling said opening with a second conductive material to form a storage node.   
     
     
       2. The method according to claim 1, wherein said first insulating layer is made of multi-layer film composed of an oxide layer, a silicon nitride layer and a plasma enhanced chemical vapor deposition(PECVD) oxide layer in this order. 
     
     
       3. The method according to claim 1, wherein said first insulating layer is made of multi-layer film composed of an oxide layer, a silicon nitride layer and a high temperature oxide(HTO) layer in this order. 
     
     
       4. The method according to claim 2 or 3, wherein said silicon nitride layer has a thickness of about 50 Å to 500 Å. 
     
     
       5. The method according to claim 2, wherein said PECVD oxide layer has a thickness of about 100 Å to 1,000 Å. 
     
     
       6. The method according to claim 3, wherein said HTO layer has a thickness of about 100 Å to 1,000 Å. 
     
     
       7. The method according to claim 1, wherein said second insulating layer comprises an oxide layer formed by PECVD method. 
     
     
       8. The method according to claim 1, wherein said second insulating layer has a thickness of about 5,000 Å to 13,000 Å. 
     
     
       9. The method according to claim 1, further comprising, after forming said storage node, removing said second insulating layer and forming a rough surface layer on an exposed portion of said storage node. 
     
     
       10. The method according to claim 9, wherein said step of removing said second insulating layer is performed by wet etch or dry etch process. 
     
     
       11. The method according to claim 9, wherein said step of forming said rough surface layer comprises growing an HSG layer.

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