US6197640B1ExpiredUtility

Semiconductor component and method of manufacture

73
Assignee: SEMICONDUCTOR COMPONENTS INDPriority: Dec 21, 1998Filed: Dec 21, 1998Granted: Mar 6, 2001
Est. expiryDec 21, 2018(expired)· nominal 20-yr term from priority
H10D 64/0133H10D 64/252H10D 30/66H10D 62/151H10D 64/518H10D 64/111H10D 30/668H10D 30/0291
73
PatentIndex Score
31
Cited by
6
References
14
Claims

Abstract

A method of manufacturing a semiconductor component includes providing a semiconductor substrate ( 200 ) having top and bottom surfaces, forming a drain electrode ( 160 ) at the bottom surface of the semiconductor substrate ( 200 ), and simultaneously forming source and gate electrodes ( 251, 254, 255, 253 ) at the first surface of the semiconductor substrate ( 200 ).

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A method of manufacturing a semiconductor component comprising: 
       providing a semiconductor substrate having a first surface and a second surface opposite the first surface;  
       forming a drain electrode of a transistor at the second surface;  
       simultaneously forming a silicon gate electrode and silicon source electrodes at the first surface of the transistor; and  
       simultaneously forming a source region while doping the silicon gate electrode and silicon source electrodes.  
     
     
       2. The method of claim  1  wherein simultaneously forming the silicon source electrodes and the silicon gate electrode further comprises: 
       depositing a silicon layer over the first surface of the semiconductor substrate; and  
       etching the silicon layer to form portions of the source electrodes and the gate electrode.  
     
     
       3. The method of claim  2  wherein etching the silicon layer to form portions of the source electrodes and the gate electrode includes separating the source electrode into two separate source electrode portions. 
     
     
       4. The method of claim  1  wherein the method of simultaneously forming the source region while doping the source and gate electrodes includes controlling the distance between the source region and a drain region. 
     
     
       5. The method of claim  4  wherein controlling the distance between the source region and the drain region includes: 
       controlling the deposition thickness of the silicon layer to create a spacer configuration for the gate electrode; and  
       forming the source region after high temperature oxidation processes have been performed in order to control lateral diffusion.  
     
     
       6. A method of manufacturing a semiconductor component exhibiting a higher frequency response comprising: 
       providing a semiconductor substrate having a first surface and a second surface opposite the first surface;  
       forming a shield electrode to block a drain region from an electric field of a silicon gate electrode;  
       forming an enhanced drain region on the first surface; and  
       forming the silicon gate electrode above the enhanced drain region such that the shield electrode separates a portion of the gate electrode from the drain region.  
     
     
       7. The method of claim  6  wherein forming the shield electrode comprises: 
       forming an oxide layer over the semiconductor substrate; and  
       forming a conductive layer over the oxide layer.  
     
     
       8. The method of claim  6  wherein forming the enhanced drain region comprises implanting ions into an epitaxial layer of the semiconductor substrate before forming the shield electrode. 
     
     
       9. The method of claim  6  wherein forming the silicon gate electrode comprises: 
       depositing a silicon layer over the first surface of the semiconductor substrate; and  
       etching the silicon layer to form the gate electrode.  
     
     
       10. A method of manufacturing a semiconductor component utilizing silicon electrodes comprising: 
       providing a semiconductor substrate having a first surface and a second surface opposite the first surface;  
       forming an active region of a first conductivity type on the first surface;  
       forming a silicon electrode in contact with the active region at a contact point;  
       diffusing a source area in the active region of a second conductivity type such that the source area below the contact point of the silicon electrode is of the second conductivity type; and  
       forming a metallic electrode in contact with the silicon electrode.  
     
     
       11. The method of claim  10  wherein forming the active region comprises implanting ions of the first conductivity type into the top surface of the semiconductor substrate through a first oxide layer and a second oxide layer. 
     
     
       12. The method of claim  10  wherein forming the silicon electrode comprises: 
       depositing a silicon layer over the first surface of the semiconductor substrate; and  
       etching the silicon layer to form a portion of the silicon electrode.  
     
     
       13. The method of claim  10  wherein diffusing the source area in the active region of a second conductivity type comprises: 
       implanting ions into the active region through an oxide layer; and  
       using the silicon electrode and a gate electrode as a self-aligned implant mask for the formation of the source region.  
     
     
       14. The method of claim  10  wherein forming a metallic electrode in contact with the silicon electrode comprises depositing a conductive interconnect layer to make contact with the silicon electrode.

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