Method of fabricating self-aligned node

Abstract

A method of fabricating a self-aligned storage node is described. A storage node plug is formed after formations of the bit line contact and the storage node contact. A spacer is formed on a sidewall of an opening, which is used for forming a bit line. The bit line is formed in the opening. Because the spacer provides good isolation, the tolerance window for forming the bit line is increased. Some follow-up steps are performed to form a storage node.

What is claimed is:  
     
       1. A method of fabricating a self-aligned storage node, comprising steps of: 
       forming a first insulating layer on a substrate;  
       forming a preserve layer on the first insulating layer;  
       forming a bit line contact and a storage node contact in the preserve layer and the first insulating layer, wherein the bit line contact and the storage node contact are in contact with a source/drain region in the substrate;  
       forming a second insulating layer on the bit line contact, the storage node contact, and the preserve layer;  
       forming a storage node plug and a cap layer in a second insulating layer, wherein the cap layer is formed on the storage node plug, and the storage node plug connects to the storage node contact;  
       patterning the second insulating layer to form a first opening that exposes the bit line contact;  
       forming a spacer on a sidewall of the first opening;  
       forming a bit line in the opening to make contact with the bit line contact;  
       forming a third insulating layer to cover the second insulating layer and the bit line; and  
       patterning the third insulating layer, the cap layer, and the second insulating layer to form a second opening exposing the storage node contact; and  
       forming a first conductive layer in the second opening.  
     
     
       2. The method of claim  1 , wherein the first insulating layer comprises a silicon oxide layer. 
     
     
       3. The method of claim  1 , wherein the second insulating layer comprises a silicon oxide layer. 
     
     
       4. The method of claim  1 , wherein a material of the storage node plug comprises polysilicon. 
     
     
       5. The method of claim  1 , wherein a material of the cap layer comprises silicon nitride. 
     
     
       6. The method of claim  1 , wherein a material of the cap layer comprises silicon-oxy-nitride. 
     
     
       7. The method of claim  1 , wherein the spacer comprises a silicon oxide layer. 
     
     
       8. The method of claim  1 , wherein the spacer comprises silicon nitride layer. 
     
     
       9. The method of claim  1 , wherein the steps of forming the bit line in the opening comprises: 
       forming a second conductive layer on the second insulating layer to fill the opening; and  
       etching back the second conductive layer to leave a portion of the second conductive layer, wherein a surface of a remaining second conductive layer is lower than the surface of the second insulating layer.  
     
     
       10. The method of claim  9 , wherein a material of the bit line comprises tungsten. 
     
     
       11. The method of claim  9 , wherein a material of the bit line comprises polycide. 
     
     
       12. A method of fabricating a bit line, comprising steps of: 
       forming a first insulating layer on a substrate;  
       forming a preserve layer on the first insulating layer;  
       forming a bit line contact and a storage node contact only in the preserve layer and the first insulating layer, wherein the bit line contact and the storage node contact are in contact with source/drain region in the substrate;  
       forming a second insulating layer to cover the bit line contact, the storage node contact, and the preserve layer;  
       forming a storage plug in the second insulating layer, wherein a cap layer is formed on the storage node plug, and the storage plug connects to the storage node contact;  
       patterning the second insulating layer to form a first opening that exposes the bit line contact, wherein the cap layer protects the storage node plug from being etched;  
       forming a spacer on a sidewall of the first opening; and  
       forming the bit line in the opening to make contact with bit line contact, wherein the spacer provides an isolation function in between the bit line and the storage node plug.  
     
     
       13. The method of claim  12 , wherein a material of the storage node plug comprises polysilicon. 
     
     
       14. The method of claim  12 , wherein a material of the cap layer comprises silicon nitride. 
     
     
       15. The method of claim  12 , wherein a material of the cap layer comprises silicon-oxy-nitride. 
     
     
       16. The method of claim  12 , wherein the spacer comprises a silicon oxide layer. 
     
     
       17. The method of claim  12 , wherein the spacer comprises a silicon nitride layer. 
     
     
       18. The method of claim  12 , wherein the steps of forming the bit line in the opening comprises: 
       forming a conductive layer on the second insulating layer to fill the opening; and  
       etching back the conductive layer to leave a portion of the conductive layer, wherein a surface of a remaining conductive layer is lower than the surface of the second insulating layer.  
     
     
       19. The method of claim  18 , wherein a material of the bit line comprises tungsten. 
     
     
       20. The method of claim  18 , wherein a material of the bit line comprises polycide.