Analog semiconductor device and method of fabricating the same

Abstract

An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device according to the present invention, includes a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; an gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.

What is claimed is:  
     
       1. An analog semiconductor device, comprising: 
       a semiconductor substrate;  
       a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively;  
       a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region;  
       an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate;  
       a gate insulating layer formed on the substrate of the transistor region;  
       a dielectric layer formed on the lower electrode;  
       a gate formed on the gate insulating layer;  
       an upper electrode of the capacitor formed on the dielectric layer.  
     
     
       2. The analog semiconductor device according to claim  1 , wherein the lower electrode is made of an impurity diffusion layer of the high concentration. 
     
     
       3. The analog semiconductor device according to claim  2 , wherein the impurity diffusion layer is N type. 
     
     
       4. The analog semiconductor device according to claim  1 , wherein the substrate is p type. 
     
     
       5. A method of fabricating an analog semiconductor device, comprising the steps of: 
       forming a mask pattern for a low electrode of a capacitor to expose a portion of the substrate;  
       forming an oxide ion-implantation layer in the substrate by ion-implanting oxide ions at a first energy;  
       forming an impurity ion-implantation layer of a high concentration over the oxide ion-implantation layer by ion-implanting impurity ions of the high concentration at a second energy being lower than the first energy;  
       removing the mask pattern;  
       annealing the substrate of a resultant structure, to form an oxide layer in the substrate and form a lower electrode of a capacitor on the oxide layer, the lower electrode being made of a diffusion layer of the high concentration;  
       forming isolating layers of trench-type in the substrate to define a transistor region and a capacitor region, respectively, the capacitor region having the oxide layer and the lower electrode;  
       forming an insulating layer and a conductive layer for gate on the overall substrate, sequentially; and  
       patterning the conductive layer for gate and the insulating layer to form a gate insulating layer and gate on the substrate of the transistor region and simultaneously form a dielectric layer and an upper electrode of the capacitor on the lower electrode of the capacitor region.  
     
     
       6. The method of fabricating the analog semiconductor device according to claim  5 , wherein the step of annealing is performed to temperature of 900 to 1,100° C. 
     
     
       7. The method of fabricating the analog semiconductor device according to claim  5 , wherein the conductive layer for the gate is made of a double layer of a doped polysilicon layer and a tungsten silicide layer. 
     
     
       8. The method of fabricating the analog semiconductor device according to claim  5 , wherein an ARC layer is further formed on the conductive layer for the gate. 
     
     
       9. The method of fabricating the analog semiconductor device according to claim  5 , wherein the substrate is p type. 
     
     
       10. The method of fabricating the analog semiconductor device according to claim  5 , wherein the impurity ion is N type.