Integrated circuit packaging structure

Abstract

An integrated circuit packaging structure, which can accommodate two or four memory chips in a single package. The feature rests upon a packaging structure that makes independent data buses between two memory chips, while implementing in parallel the address buses and control buses, and finally encapsulates them within one package in the expectation of doubling the memory capacity without increasing the size of the package and the number of pins.

What is claimed is:  
     
       1. An integrated circuit packaging structure including at least two dice, the address bus of one of the dice being connected electrically to the address bus of the other one of the dice, while the control bus of one of the dice is connected electrically to the control bus of the other one of the dice, the integrated circuit packaging structure further comprising: 
       a printed circuit board unit having a top surface formed with a plurality of electrical traces, a plurality of bonding pads provided on the top surface and connected electrically to a corresponding one of the electrical traces, and an aperture formed therethrough;  
       each of the dice having an upper surface and a plurality of bonding pads formed on the upper surface, the upper surface of each of the dice being attached to a bottom surface of the printed circuit board unit such that the bonding pads of the dice are registered with the aperture; and  
       a plurality of conductive wires interconnecting the bonding pads of the dice and the bonding pads of the printed circuit board unit through the aperture.  
     
     
       2. An integrated circuit packaging structure as claimed in claim  1 , further comprising an encapsulation layer formed on the bottom surface of the printed circuit board unit around the dice. 
     
     
       3. An integrated circuit packaging structure as claimed in claim  1 , wherein the printed circuit board unit includes superimposed upper and lower printed circuit boards, the upper printed circuit board having a top surface which serves as the top surface of the printed circuit board unit, and a bottom surface, the lower printed circuit board having a top surface attached to the bottom surface of the upper printed circuit board, a bottom surface on which a plurality of bonding pads are provided, and a hole formed therethrough, the lower printed circuit board further having an inner peripheral wall which confines the hole, the inner peripheral wall of the lower printed circuit board and the bottom surface of the upper printed circuit board cooperatively defining therebetween a die-receiving cavity in which the dice are received, the integrated circuit packaging structure further comprising: 
       at least two second dice, each of which being received in the die-receiving cavity and having a bottom surface attached to a bottom surface of a corresponding one of the first dice, each of the second dice further having a top surface on which a plurality of bonding pads are mounted; and  
       a plurality of second conductive wires interconnecting the bonding pads of the second dice and the bonding pads of the lower printed circuit board.