US6258287B1ExpiredUtility

Method and apparatus for low energy electron enhanced etching of substrates in an AC or DC plasma environment

83
Assignee: GEORGIA TECH RES INSTPriority: Aug 28, 1996Filed: Sep 17, 1997Granted: Jul 10, 2001
Est. expiryAug 28, 2016(expired)· nominal 20-yr term from priority
H01J 2237/3345H01J 37/32623H01J 37/3233H01J 37/32027H01J 37/32018H01J 37/32596B08B 7/0035
83
PatentIndex Score
33
Cited by
31
References
18
Claims

Abstract

A method of low-damage, anisotropic etching of substrates including mounting the substrate upon a mechanical support located within an ac or dc plasma reactor. The mechanical support is independent of the plasma reactor generating apparatus and capable of being electrically biased. The substrate is subjected to a plasma of low-energy electrons and a species reactive with the substrate. An additional structure capable of being electrically biased can be placed within the plasma to control further the extraction or retardation of particles from the plasma.

Claims

exact text as granted — not AI-modified
The following is claimed:  
     
       1. A process for low-damage anisotropic dry etching of a substrate, comprising the steps of: 
       placing a substrate on a mechanical support within a plasma reactor, said mechanical support isolated from the creation of the plasma, said plasma including low energy electrons having a kinetic energy less than about 100 eV and at least one species reactive with the substrate; and  
       directing said low energy electrons and said reactive species onto the substrate.  
     
     
       2. The process of claim  1 , further comprising the step of selecting said substrate from the group consisting of Group III-V semiconductors, Group IV semiconductors, Group II-VI semiconductors, metals, alloys of the foregoing, superconductors, polymers, and insulating substrates. 
     
     
       3. The process of claim  1 , wherein said plasma reactor generates a dc plasma. 
     
     
       4. The process of claim  1 , wherein said plasma reactor generates an ac plasma. 
     
     
       5. The process of claim  1 , wherein said mechanical support is electrically biased, said mechanical support imparting said electrical bias upon the substrate. 
     
     
       6. The process of claim  5 , wherein said mechanical support imparts a dc electrical bias upon the substrate. 
     
     
       7. The process of claim  5 , wherein said mechanical support imparts an ac bias upon the substrate. 
     
     
       8. The process of claim  5 , wherein said mechanical support imparts both a dc and an ac bias upon the substrate. 
     
     
       9. The process of claim  5 , further comprising the step of periodically modulating said electrical bias of said mechanical support to a value below the value of the electrical potential of the plasma. 
     
     
       10. The process of claim  1 , further comprising the step of including an additional structure within said plasma, said additional structure capable of being electrically biased. 
     
     
       11. The process of claim  10 , wherein said additional structure is dc electrically biased. 
     
     
       12. The process of claim  10 , wherein said additional structure is ac electrically biased. 
     
     
       13. The process of claim  10 , wherein said additional structure is both ac and dc electrically biased. 
     
     
       14. A process for low-damage anisotropic dry etching of a substrate, comprising the steps of: 
       providing a direct current plasma reactor including a cathode and an anode;  
       placing a semiconductor on the anode of the direct current plasma reactor;  
       generating low energy electrons with a cold cathode;  
       subjecting the semiconductor to a plasma including low energy electrons and a species reactive with the semiconductor; and  
       placing an additional structure within said plasma, said additional structure capable of being electrically biased.  
     
     
       15. The process of claim  14 , further comprising the step of selecting said substrate from the group consisting of Group III-V semiconductors, Group IV semiconductors, and Group II-VI semiconductors. 
     
     
       16. The process of claim  14 , wherein said additional structure is dc electrically biased. 
     
     
       17. The process of claim  14 , wherein said additional structure is ac electrically biased. 
     
     
       18. The process of claim  14 , wherein said additional structure is both ac and dc electrically biased.

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