Method for removing anti-reflective coating layer using plasma etch process before contact CMP

Abstract

The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH 3 F)/oxygen (O 2 ) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH 3 F/O 2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.

The invention claimed is:  
     
       1. A method of manufacturing a semiconductor device on a semiconductor substrate, comprising the steps of: 
       forming a multi-layer structure on an active region on the semiconductor substrate;  
       forming a source region and a drain region on said active region adjacent said sidewall spacers;  
       forming sidewall spacers around said multi-layer structure;  
       forming a dielectric layer over the semiconductor substrate, including said multi-layer structure, said sidewall spacers, said source region and said drain region, said dielectric layer having a top surface;  
       forming an anti-reflective coating layer over said dielectric layer;  
       forming a masking layer over said anti-reflective coating layer;  
       patterning said masking layer to form a contact mask;  
       forming a first opening and a second opening in said dielectric layer through said anti-reflective coating layer using said contact mask as a mask, said first opening exposes a portion of said source region and said second opening exposes a portion of said drain region; and  
       removing said anti-reflective coating layer using selective plasma etch to etch said anti-reflective coating layer with reactive ions at a rate which is significantly faster than the etch rates of said dielectric layer, said source region, and said drain region.  
     
     
       2. The method as claimed in claim  1  wherein said multi-layer structure comprises a gate dielectric layer, a floating gate disposed on said gate dielectric layer, an inter-gate dielectric disposed on said floating gate, a control gate disposed on said inter-gate dielectric, and a silicide layer disposed on said control gate. 
     
     
       3. The method as claimed in claim  2  wherein said multi-layer structure comprises a polysilicon layer disposed on said silicide layer, and a passivation layer disposed on said polysilicon layer, said passivation layer comprises a material selected from the group consisting of nitride and oxynitride. 
     
     
       4. The method as claimed in claim  1  wherein said step of removing said anti-reflective coating layer is about fifteen times faster than the etch rates of said dielectric layer. 
     
     
       5. The method as claimed in claim  1  wherein said dielectric layer comprises boro-phospho-tetra-ethyl-ortho silicate (BPTEOS). 
     
     
       6. The method as claimed in claim  1  wherein said anti-reflective coating layer comprises a nitride. 
     
     
       7. The method as claimed in claim  1  wherein said anti-reflective coating layer comprises an oxynitride. 
     
     
       8. The method as claimed in claim  1  wherein said anti-reflective coating layer is formed to a thickness below 1100 angstroms. 
     
     
       9. The method as claimed in claim  1  wherein the step of removing said anti-reflective coating layer using selective plasma etch uses a plasma comprising fluoromethane and oxygen. 
     
     
       10. The method as claimed in claim  1  further including the steps of: 
       filling said first opening and said second opening with a conductive material; and  
       planarizing said conductive material smooth with said top surface of said dielectric layer.  
     
     
       11. The method as claimed in claim  10  wherein said conductive material is selected from a group consisting of tungsten, tantalum, titanium, copper, aluminum, silver, gold, an alloy thereof, polysilicon, and a compound thereof. 
     
     
       12. A method of manufacturing a semiconductor device on a semiconductor substrate, comprising the steps of: 
       forming a multi-layer structure on an active region on the semiconductor substrate;  
       forming a source region and a drain region on said active region adjacent said sidewall spacers;  
       forming sidewall spacers around said multi-layer structure;  
       forming a dielectric layer over the semiconductor substrate, including said multi-layer structure, said sidewall spacers, said source region and said drain region, wherein said dielectric layer comprises boro-phospho-tetra-ethyl-ortho silicate (BPTEOS), said dielectric layer having a top surface;  
       forming an anti-reflective coating layer over said dielectric layer;  
       forming a masking layer over said anti-reflective coating layer, wherein said anti-reflective coating layer comprises a nitride;  
       patterning said masking layer to form a contact mask;  
       forming a first opening and a second opening in said dielectric layer through said anti-reflective coating layer using said contact mask as a mask, said first opening exposes a portion of said source region and said second opening exposes a portion of said drain region; and  
       removing said anti-reflective coating layer using selective plasma etch with a plasma comprising fluoromethane and oxygen to etch said anti-reflective coating layer with reactive ions at a rate which is significantly faster than the etch rates of said dielectric layer, said source region, and said drain region.  
     
     
       13. The method as claimed in claim  12  wherein said multi-layer structure comprises a gate dielectric layer, a floating gate disposed on said gate dielectric layer, an inter-gate dielectric disposed on said floating gate, a control gate disposed on said inter-gate dielectric, and a silicide layer disposed on said control gate. 
     
     
       14. The method as claimed in claim  12  wherein said multi-layer structure comprises a polysilicon layer disposed on said silicide layer, and a passivation layer disposed on said polysilicon layer, said passivation layer comprises a material selected from the group consisting of nitride and oxynitride. 
     
     
       15. The method as claimed in claim  12  wherein said step of removing said anti-reflective coating is about fifteen times the etch rate of said dielectric layer. 
     
     
       16. The method as claimed in claim  12  wherein said anti-reflective coating layer consists of a material selected from a group consisting of silicon oxynitride, silicon nitride, and a combination thereof. 
     
     
       17. The method as claimed in claim  12  wherein said anti-reflective coating layer is formed to a thickness in the range around 300 to 1100 angstroms. 
     
     
       18. The method as claimed in claim  12  further including the steps of: 
       filling said first opening, said second opening, and said third opening with a conductive material, wherein said conductive material is selected from a group consisting of tungsten, tantalum, titanium, copper, aluminum, silver, gold, an alloy thereof, polysilicon, and a compound thereof; and  
       planarizing said conductive material smooth with said top surface of said dielectric layer.  
     
     
       19. A method of manufacturing a semiconductor device on a semiconductor substrate, comprising the steps of: 
       forming a multi-layer structure on an active region on the semiconductor substrate, wherein said multi-layer structure comprises a gate dielectric layer, a floating gate disposed on said gate dielectric layer, an inter-gate dielectric disposed on said floating gate, a control gate disposed on said inter-gate dielectric, a silicide layer disposed on said control gate, a polysilicon layer disposed on said silicide layer, and a passivation layer disposed on said polysilicon layer, said passivation layer comprises a material selected from the group consisting of nitride and oxynitride;  
       forming a source region and a drain region on said active region adjacent said sidewall spacers;  
       forming sidewall spacers around said multi-layer structure;  
       forming a dielectric layer over the semiconductor substrate, including said multi-layer structure, said sidewall spacers, said source region and said drain region, said dielectric layer having a top surface;  
       forming an anti-reflective coating layer over said dielectric layer;  
       forming a masking layer over said anti-reflective coating layer;  
       patterning said masking layer to form a contact mask;  
       forming a first opening, a second opening and a third opening in said dielectric layer through said anti-reflective coating layer using said contact mask as a mask, said first opening exposes a portion of said source region, said second opening exposes a portion of said drain region, and said third opening exposes a portion of silicide layer; and  
       removing said anti-reflective coating layer using selective plasma etch to etch said anti-reflective coating layer with reactive ions at a rate which is significantly faster than the etch rates of said dielectric layer, said source region, said drain region, and said silicide layer.  
     
     
       20. The method as claimed in claim  19  wherein said step of removing said anti-reflective coating layer is about fifteen times faster than the etch rate of said dielectric layer. 
     
     
       21. The method as claimed in claim  19  wherein said dielectric layer comprises boro-phospho-tetra-ethyl-ortho silicate (BPTEOS). 
     
     
       22. The method as claimed in claim  19  wherein said anti-reflective coating layer is formed to a thickness in the range around 300 to 1100 angstroms. 
     
     
       23. The method as claimed in claim  19  wherein the step of removing said anti-reflective coating layer using selective plasma etch uses a plasma comprising fluoromethane and oxygen. 
     
     
       24. The method as claimed in claim  19  further including the steps of: 
       filling said first opening, said second opening, and said third opening with a conductive material, wherein said conductive material is selected from a group consisting of tungsten, tantalum, titanium, copper, aluminum, silver, gold, an alloy thereof, polysilicon, and a compound thereof; and  
       planarizing said conductive material smooth with said top surface of said dielectric layer.