Method of preventing neck oxidation of a storage node

Abstract

A silicon oxide layer is formed on a substrate surface of a semiconductor wafer. A node contact is formed in the silicon oxide layer. A storage node is formed on the silicon oxide layer and connects to the node contact. An ion implantation process is performed as a surface process on the silicon oxide layer. A silicon nitride layer is subsequently formed on the surfaces of the silicon oxide layer and the storage node. Finally, a high-temperature oxidation process is performed. The surface process reduces the difference in the incubation time for the silicon nitride layer deposited on the silicon oxide layer and on the surface of the storage node. The surface process also relieves problems associated with the nonuniformity in thickness of the silicon nitride layer. Neck-oxidation at the interface of the storage node and the node contact is thus prevented.

What is claimed is:  
     
       1. A method of preventing neck-oxidation phenomena in a storage node of a capacitor element of a dynamic random access memory (DRAM) cell, a node contact of the storage node disposed on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, a silicon oxide layer above the surface of the silicon substrate, and a node contact in the silicon oxide layer, the node contact connected to the storage node, the method comprising: 
       performing a surface process on the silicon oxide layer, the surface process utilizing an ion implantation process; and  
       forming a silicon nitride layer on the surfaces of the silicon oxide layer and the storage node;  
       wherein the surface process will decrease both the difference in the incubation time and the difference in the thickness between the silicon nitride layer formed above the silicon oxide layer surface and the storage node surface, and prevents the neck-oxidation phenomenon at the interface of the storage node and the node contact.  
     
     
       2. The method of claim  1  wherein the surface of the storage node is rough and comprises a plurality of hemispherical grain (HSG) structures. 
     
     
       3. The method of claim  1  wherein dopants in the ion implantation process are silicon atoms or silicon ions, the dopants forming a silicon-rich structure of a silicon oxide compound on the surface of the silicon oxide layer. 
     
     
       4. The method of claim  3  wherein the energy in the ion implantation process is less than 40 keV, and the dosage of dopants is greater than 2×10 15  cm −2 . 
     
     
       5. The method of claim  1  wherein dopants in the ion implantation process are nitrogen atoms or nitrogen ions. 
     
     
       6. A method of fabricating a cell dielectric layer of a capacitor, the method comprising: 
       providing a semiconductor wafer, the semiconductor wafer comprising a substrate, a silicon oxide layer disposed above the substrate surface, a node contact in the silicon oxide layer and approximately level with the top surface of the silicon oxide layer, and a storage node disposed above the silicon oxide layer and connected to the node contact;  
       performing a surface process on the silicon oxide layer, the surface process utilizing an ion implantation process;  
       forming a silicon nitride layer on the surfaces of the silicon oxide layer and the storage node; and  
       performing a high-temperature oxidation process.  
     
     
       7. The method of claim  6  wherein the surface of the storage node is rough and comprises a plurality of hemispherical grain (HSG) structures. 
     
     
       8. The method of claim  7  wherein the surface of each HSG structure comprises a native oxide layer, and the thickness of the native oxide layer is approximately 10 to 50 angstroms (Å). 
     
     
       9. The method of claim  6  wherein dopants in the ion implantation process are silicon atoms or silicon ions, the dopants forming a silicon-rich structure of a silicon oxide compound on the surface of the silicon oxide layer. 
     
     
       10. The method of claim  9  wherein the energy in the ion implantation process is less than 40 keV, and the dosage of dopants is greater than 2×10 15  cm −2 . 
     
     
       11. The method of claim  6  wherein dopants in the ion implantation process are nitrogen atoms or nitrogen ions. 
     
     
       12. The method of claim  6  wherein the surface process decreases both the incubation time difference and the thickness difference between the silicon nitride layer formed above the silicon oxide layer surface and the storage node surface, and prevents neck-oxidation phenomena at the interface of the storage node and the node contact during the high-temperature oxidation process.