Method and apparatus for forming a junctionless antifuse

Abstract

A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

What is claimed is:  
     
       1. An antifuse, comprising: 
       a substrate;  
       a field oxide on the substrate;  
       a first conductive island on the field oxide;  
       a second conductive island on the field oxide, the second conductive island being separate from the first conductive island;  
       a first contact connected to the first conductive island;  
       a second contact connected to the second conductive island;  
       a first conductive layer on the first conductive island;  
       a programming layer on the first conductive layer and connected to both the first contact and the second contact; and  
       a second conductive layer on the programming layer and connected to the first contact.  
     
     
       2. The antifuse of claim  1 , wherein the first conductive layer is free of contact with the first contact and the second contact. 
     
     
       3. The antifuse of claim  1 , wherein the first contact is free of contact with the first conductive layer and the second conductive layer. 
     
     
       4. The antifuse of claim  1 , wherein the first conductive island includes a polysilicon layer and a silicide layer. 
     
     
       5. The antifuse of claim  4 , wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component. 
     
     
       6. The antifuse of claim  1 , wherein the second conductive island includes a polysilicon layer and a silicide layer. 
     
     
       7. The antifuse of claim  1 , wherein the first conductive island consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component. 
     
     
       8. An antifuse having a blown state and an unblown state, comprising: 
       a substrate;  
       a field oxide on the substrate;  
       a first conductive island on the field oxide;  
       a second conductive island on the field oxide, the second conductive island being separate from the first conductive island;  
       a first contact connected to the first conductive island;  
       a second contact connected to the second conductive island;  
       a first conductive layer on the first conductive island;  
       a programming layer on the first conductive layer and connected to both the first contact and the second contact;  
       a second conductive layer on the programming layer and connected to the first contact;  
       wherein a first current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first conductive island, and the first contact in the unblown state; and  
       wherein a second current path consists of the first contact, the programmable layer, and the second contact in the blown state.  
     
     
       9. The antifuse of claim  8 , wherein the first conductive layer is free of contact with the first contact and the second contact. 
     
     
       10. The antifuse of claim  8 , wherein the first contact is free of contact with the first conductive layer and the second conductive layer. 
     
     
       11. The antifuse of claim  8 , wherein the first conductive island includes a polysilicon layer and a silicide layer. 
     
     
       12. The antifuse of claim  11 , wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component. 
     
     
       13. The antifuse of claim  8 , wherein the second conductive island includes a polysilicon layer and a silicide layer. 
     
     
       14. The antifuse of claim  8 , wherein the first conductive island consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component. 
     
     
       15. An antifuse, consisting of: 
       a substrate;  
       a field oxide on the substrate;  
       a first conductive island on the field oxide;  
       a second conductive island on the field oxide, the second conductive island being separate from the first conductive island;  
       a first contact connected to the first conductive island;  
       a second contact connected to the second conductive island;  
       a first conductive layer on the first conductive island;  
       a programming layer on the first conductive layer and connected to both the first contact and the second contact; and  
       a second conductive layer on the programming layer and connected to the first contact.  
     
     
       16. The antifuse of claim  15 , wherein the first conductive layer is free of contact with the first contact and the second contact. 
     
     
       17. The antifuse of claim  15 , wherein the first contact is free of contact with the first conductive layer and the second conductive layer. 
     
     
       18. The antifuse of claim  15 , wherein the first conductive island includes a polysilicon layer and a silicide layer. 
     
     
       19. The antifuse of claim  18 , wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component. 
     
     
       20. The antifuse of claim  15 , wherein the second conductive island includes a polysilicon layer and a silicide layer. 
     
     
       21. The antifuse of claim  15 , wherein the first conductive island consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component. 
     
     
       22. The antifuse of claim  15 , wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first conductive island, and the first contact. 
     
     
       23. The antifuse of claim  22 , wherein a blown current path consists of the first contact, the programmable layer, and the second contact. 
     
     
       24. An antifuse, comprising: 
       a substrate having a surface;  
       a field oxide on the surface;  
       a first conductive island on the field oxide;  
       a second conductive island on the field oxide, the second conductive island being separate from the first conductive island;  
       a first contact connected to the first conductive island, the first contact extending outwardly relative to the surface;  
       a second contact connected to the second conductive island, the second contact extending outwardly relative to the surface;  
       a first conductive layer on the first conductive island;  
       a programming layer on the first conductive layer and connected to both the first contact and the second contact; and  
       a second conductive layer on the programming layer and connected to the first contact.  
     
     
       25. The antifuse of claim  24 , wherein the first conductive layer is free of contact with the first contact and the second contact. 
     
     
       26. The antifuse of claim  24 , wherein the first contact is free of contact with the first conductive layer and the second conductive layer. 
     
     
       27. The antifuse of claim  24 , wherein the first conductive island includes a polysilicon layer and a silicide layer. 
     
     
       28. The antifuse of claim  24 , wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component. 
     
     
       29. The antifuse of claim  28 , wherein the second conductive island includes a polysilicon layer and a silicide layer. 
     
     
       30. The antifuse of claim  28 , wherein the first conductive island consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component. 
     
     
       31. The antifuse of claim  28 , wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first conductive island, and the first contact. 
     
     
       32. The antifuse of claim  29 , wherein a blown current path consists of the first contact, the programmable layer, and the second contact. 
     
     
       33. An antifuse, comprising: 
       a substrate;  
       a field oxide on the substrate;  
       a first conductive island on the field oxide;  
       a second conductive island on the field oxide, the second conductive island being separate from the first conductive island;  
       a first contact connected to the first conductive island;  
       a second contact connected to the second conductive island;  
       a first conductive layer on the first conductive island;  
       a programming layer on the first conductive layer and connected to both the first contact and the second contact;  
       a second conductive layer on the programming layer and connected to the first contact;  
       wherein the first conductive island is in electrically-conductive contact with only the first conductive layer and the first contact.  
     
     
       34. The antifuse of claim  33 , wherein an insulative material and the field oxide electrically insulate the first conductive island. 
     
     
       35. The antifuse of claim  33 , wherein an insulative material and the field oxide electrically insulate the second conductive island. 
     
     
       36. The antifuse of claim  33 , wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first conductive island, and the first contact. 
     
     
       37. The antifuse of claim  33 , wherein a blown current path consists of the first contact, the programmable layer, and the second contact. 
     
     
       38. An antifuse, comprising: 
       a substrate;  
       a field oxide on the substrate;  
       a first conductive island directly on the field oxide;  
       a second conductive island directly on the field oxide, the second conductive island being separate from the first conductive island;  
       a first contact connected to the first conductive island;  
       a second contact connected to the second conductive island;  
       a first conductive layer contacting the first conductive island;  
       a programming layer contacting the first conductive layer and connected to both the first contact and the second contact; and  
       a second conductive layer contacting the programming layer and connected to the first contact.  
     
     
       39. The antifuse of claim  38 , wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first conductive island, and the first contact. 
     
     
       40. The antifuse of claim  38 , wherein a blown current path consists of the first contact, the programmable layer, and the second contact.