Hermetically sealed chip scale packages formed by wafer level fabrication and assembly

Abstract

Integrated circuit devices produced by a method in which devices are formed and packaged at the wafer scale. The integrated circuit device includes bond pads on a first side thereof, a layer of glass adhesively affixed to the first side, a layer of sealant covering the second side and edges thereof, and a metallization pattern on the layer of glass connected via an array of contact holes to the bond pads on the integrated circuit device. The device is advantageously formed with an etchable glass package and palladium metallization pattern.

What is claimed is:  
     
       1. A semiconductor device, comprising: 
       a semiconductor die having first and second sides, a peripheral edge, and a circuit therein connected to an array of bond pads on said first side;  
       a first layer of glass comprising a plate of photo-etchable glass attached with adhesive to said first side;  
       an array of conductor filled contact holes extending through said first layer of glass from said array of bond pads to an exterior surface of said first layer of glass;  
       a metallization pattern on said exterior surface of said first layer of glass, said metallization pattern including a plurality of conductive interconnections, each said conductive interconnection comprising a lead connected to at least one of said conductor filled contact holes, said metallization pattern comprising one of palladium and a palladium alloy;  
       an insulative sealant layer covering said second side and edge of said die.  
     
     
       2. The semiconductor device of claim  1 , wherein said insulative sealant layer comprises a hardened layer of spin-on-glass. 
     
     
       3. The semiconductor device of claim  1 , wherein said insulative sealant layer comprises a polymeric sealant material. 
     
     
       4. The semiconductor device of claim  1 , wherein said insulative sealant layer comprises a plate of glass adhesively attached to said second side of said die. 
     
     
       5. The semiconductor device of claim  1 , wherein said conductor filled contact holes are substantially linear. 
     
     
       6. The semiconductor device of claim  1 , further comprising a coat of silicon nitride applied to portions of said device for sealing thereof.