Edge-triggered scan flip-flop and one-pass scan synthesis methodology

Abstract

An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.

What is claimed is:  
     
       1. A scan flip-flop comprising: 
       a data-in signal input, a scan-in signal input, and a test signal input;  
       a data-out signal output and a scan-out signal output, the data-out signal output being formed by a data-out signal driver and the scan-out Signal output being formed by a scan-out signal driver, the scan-out signal driver being a weak signal driver; and  
       the data-out signal output and the scan-out signal output being coupled to the data-in signal input when the test signal input is provided a signal of a first value, and the data-out signal output and the scan-out signal output being coupled to the scan-in signal input when the test signal input is provided a signal of a second valve.  
     
     
       2. The scan flip-flop of  claim 1  wherein the weak signal driver has an input and an output, with the input being the data-out signal output and the output the scan-out signal output. 
     
     
       3. The scan flip-flop of  claim 2  wherein the weak signal driver provides a substantially constant load to the data-out signal driver. 
     
     
       4. The scan flip-flop of  claim 3  further comprising a circuit element between the data-out signal driver and the weak signal driver, the circuit element providing a substantially constant load to the data-out signal driver. 
     
     
       5. The scan flip-flop of  claim 4  wherein the circuit element provides a signal delay. 
     
     
       6. The scan flip-flop of  claim 5  wherein the circuit element and the weak signal driver comprise inverters. 
     
     
       7. The scan flip-flop of  claim 5  wherein the circuit element comprises at least one inverter and the weak signal driver comprises one of a group of an inverter and a buffer. 
     
     
       8. The scan flip-flop of  claim 5  wherein the test signal input comprises a test clock signal. 
     
     
       9. The scan flip-flop of  claim 8  further comprising an input clock signal. 
     
     
       10. The scan flip-flop of  claim 9  wherein when the input clock signal is set to a first clock value the data-out signal and the scan-out signal are set to the data-in signal, when the input clock signal is set to a second clock value and the test clock signal is set to a first test clock value the data-out signal and the scan-out signal are set to the scan-in signal, and when the input clock signal is not set to the first clock value and the test clock signal is not set to the first test clock value the data-out signal and the scan-out signal do not change values. 
     
     
       11. The scan flip-flop of  claim 9  wherein when the input clock signal is set to a first clock value the data-out signal and the scan-out signal are set to the complement of the data-in signal, when the input clock signal is set to a second clock value and the test clock signal is set to a first test clock value the data-out signal and the scan-out signal are set to the complement of the scan-in signal, and when the input clock signal is not set to the first clock value and the test clock signal is not se t to the first test clock value the data-out signal and the scan-out signal do not change values. 
     
     
       12. The scan flip-flop of  claim 5  wherein the test signal input comprises a test mode signal. 
     
     
       13. The scan flip-flop of  claim 12  further comprising an input clock signal. 
     
     
       14. The scan flip-flop of  claim 13  wherein when the input clock signal is set to a first clock value and the test mode signal is set to a TEST value the data-out signal and the scan-out signal are set to the data-in signal, when the input clock signal is set to a first clock value and the test mode signal is set to a {overscore (TEST)} value the data-out signal and the scan-out signal are set to the scan-in signal, and when the input clock signal is not set to the first clock value the data-out signal and the scan-out signal do not change. 
     
     
       15. The scan flip-flop of  claim 13  wherein when the input clock signal is set to a first clock value and the test mode signal is set to a TEST value the data-out signal and the scan-out signal are set to the complement of the data-in signal, when the input clock signal is set to a first clock value and the test mode signal is set to a TEST value the data-out signal and the scan-out signal are set to the complement of the scan-in signal, and when the input clock signal is not set to the first clock value the data-out signal and the scan-out signal do not change. 
     
     
       16. A scan flip-flop comprising; 
       a multiplexer with a data input, a scan input, a control input, and a multiplexer output;  
       a transfer gate with a transfer gate input, a transfer gate output, and at least one clock control signal input, the transfer gate input being coupled to the multiplexer output;  
       a first latch with a first latch input and a first latch output, the first latch input being coupled to the transfer gate output;  
       a data out signal driver with a data out signal driver input and a data output, the data out signal driver input being coupled to the first latch output; and  
       a scan out signal driver with a scan out signal driver input and a scan output, the scan out signal driver input being coupled to the data output, and the scan out signal driver being a weak signal driver.  
     
     
       17. The scan flip-flop of  claim 16  further comprising: 
       a second latch with a second latch input and a second latch output, with the second latch input being coupled to the first latch output and the data-out signal driver input being coupled to the second latch output.  
     
     
       18. A scan flip-flop comprising: 
       a multiplexer with a data input, a scan input, a control input, and a multiplexer output;  
       a transfer gate with a transfer gate input, a transfer gate output, and at least one clock control signal input, the transfer gate input being coupled to the multiplexer output;  
       a latch with a latch input and a latch output, the latch input being coupled to the transfer gate output;  
       a data out signal driver with a data out signal driver input and a data output, the data out signal driver input being coupled to the latch output;  
       a circuit delay element with a circuit delay element input and a circuit delay element output, the circuit delay element input being coupled to the data out signal driver; and  
       a scan out signal driver with a scan out signal driver input and a scan output, the scan out signal driver being a weak signal driver, the scan out signal driver input being coupled to the circuit delay element output.  
     
     
       19. The scan flip-flop of  claim 18  wherein the circuit delay element comprises at least one buffer. 
     
     
       20. The scan flip-flop of  claim 18  wherein the circuit delay element comprises at least one inverter. 
     
     
       21. The scan flip-flop of  claim 18  wherein the circuit delay element comprises simple logic gates. 
     
     
       22. A method of creating a digital electronic circuit design with scan flip-flops comprising: 
       providing a high level language description representing the digital electronic circuit;  
       generating a list including logic components and interconnections between the logic components from the high level language description, the list of logic components including a plurality of flip-flop components;  
       mapping the logic components to cells specifying electronic circuit components, including mapping the flip-flop components to at least one scan flip-flop cell, the scan flip-flop cell specifying a flip-flop element having at least two inputs, a data input and a scan input, and at least two outputs, a data output and a scan output, with the data output driven by a data output signal driver and the scan output driven by a scan output signal driver, the scan output signal driver being a weak signal driver, the scan output signal driver receiving a signal from the data output signal driver, and the scan output signal driver presenting a substantially known load to the data output signal driver; and  
       forming a representation of a scan chain by linking a data output of a first of the plurality of scan flip-flop cells to a scan input of a second of the plurality of scan flip-flop cells.  
     
     
       23. The method of  claim 22  wherein the scan flip-flop cell further specifies that the scan output signal driver receives the signal from the data output driver by way of a data output signal driver to scan output signal path, the signal path including at least one circuit delay element. 
     
     
       24. A method using a computer for designing a digital electronic circuit including scan flip-flops forming a scan chain based on a high level language description describing the functions of the digital electronic circuit comprising: 
       generating a list including logic components and interconnections between the logic components from the high level language description, the list of logic components including a plurality of flip-flop components;  
       mapping the logic components to cells specifying electronic circuit components, including mapping the flip-flop components to at least one scan flip-flop cell, the scan flip-flop cell specifying a flip-flop element having at least two inputs, a data input and a scan input, and at least two outputs, a data output and a scan output, with the data output driven by a data output signal driver and the scan output driven by a scan output signal driver, the scan output signal driver being a weak signal driver, the scan output signal driver receiving a signal from the data output signal driver, and the scan output signal driver presenting a substantially known load to the data output signal driver; and  
       forming a representation of a scan chain by linking a data output of a first of the plurality of scan flip-flop cells to a scan input of a second of the plurality of scan flip-flop cells.  
     
     
       25. A scan flip-flop comprising: 
       a data-in signal input, a scan-in signal input, and a test signal input;  
       a data-out signal output and a scan-out signal output, the data-out signal output being formed by a data-out signal driver and the scan-out signal output being formed by a scan-out signal driver, the scan output signal driver being a weak signal driver;  
       the data-out signal output and the scan-out signal output being coupled to the data-in signal input when the test signal input is provided a signal of a first value, and the data-out signal output and the scan-out signal output being coupled by a signal path to the scan-in signal input when the test mode input is provided a signal of a second value, with the signal path having delay elements.  
     
     
       26. A scan flip-flop comprising: 
       a multiplexer with a data input, a scan input, a control input, a circuit delay element, and a multiplexer output, the multiplexer output being linked to the data input when the control input is a first value and the multiplexer output being linked to the circuit delay element, which is linked to the scan input, when the control input is a second value;  
       a transfer gate with a transfer gate input, a transfer gate output, and at least one clock control signal input, the transfer gate input being coupled to the multiplexer output;  
       a latch with a latch input and a latch output, the latch input being coupled to the transfer gate output;  
       a data out signal driver with a data out signal driver input and a data output, the data out signal driver input being coupled to the latch output; and  
       a scan out signal driver with a scan out signal driver input and a scan output, the scan output signal driver being a weak signal driver, the scan out signal driver input being coupled to the latch output.  
     
     
       27. The scan flip-flop of  claim 26  further comprising a second latch with a second latch input and a second latch output, with the second latch input being coupled to the latch output and the data-out signal driver input being coupled to the second latch output.