Inventor · disambiguated record
Kenneth D. Wagner
Also filed as: WAGNER KENNETH · WAGNER KENNETH D · WAGNER KENNETH DAVID
15 granted patents·527 citations·filing 1992–2018
94Inventor score
Top patents by PatentIndex Score
15 records- 0194US5696771AMethod and apparatus for performing partial unscan and near full scan within design for test applicationsSYNOPSYS INC·Filed 1996·Granted Dec 9, 1997·112 cites·32 claims
- 0293US9922524B2Methods for detecting and handling fall and perimeter breach events for residents of an assisted living facilityBLUE WILLOW SYSTEMS INC·Filed 2016·Granted Mar 20, 2018·42 cites·16 claims
- 0393US5612963AHybrid pattern self-testing of integrated circuitsIBM·Filed 1995·Granted Mar 18, 1997·108 cites·13 claims
- 0485US6067650AMethod and apparatus for performing partial unscan and near full scan within design for test applicationsSYNOPSYS INC·Filed 1997·Granted May 23, 2000·54 cites·16 claims
- 0584US9779197B1Method and system of merging memory cells into multi-bit registers in an integrated circuit layoutMICROSEMI SOLUTIONS (U S ) INC·Filed 2015·Granted Oct 3, 2017·12 cites·19 claims
- 0682US6389566B1Edge-triggered scan flip-flop and one-pass scan synthesis methodologyS3 INC·Filed 1998·Granted May 14, 2002·57 cites·27 claims
- 0781US6169418B1Efficient routing from multiple sources to embedded DRAM and other large circuit blocksS3 INC·Filed 1998·Granted Jan 2, 2001·40 cites·33 claims
- 0879US8533546B1Reconfigurable scan chain connectivity to enable flexible device I/O utilizationFERGUSON KENNETH WILLIAM·Filed 2011·Granted Sep 10, 2013·8 cites·19 claims
- 0970US5633812AFault simulation of testing for board circuit failuresIBM·Filed 1992·Granted May 27, 1997·36 cites·8 claims
- 1069US6158033AMultiple input signature testing & diagnosis for embedded blocks in integrated circuitsS3 INC·Filed 1998·Granted Dec 5, 2000·32 cites·14 claims
- 1165US10198927B2Methods for detecting and handling fall and perimeter breach events for residents of an assisted living facilityBLUE WILLOW SYSTEMS INC·Filed 2018·Granted Feb 5, 2019·1 cites·20 claims
- 1263US5375091AMethod and apparatus for memory dynamic burn-in and testIBM·Filed 1993·Granted Dec 20, 1994·23 cites·22 claims
- 1362US9104825B1Method of reducing current leakage in a product variant of a semiconductor devicePMC SIERRA US INC·Filed 2014·Granted Aug 11, 2015·2 cites·21 claims
- 1457US10607469B2Methods for detecting and handling fall and perimeter breach events for residents of an assisted living facilityPHILIPS NORTH AMERICA LLC·Filed 2018·Granted Mar 31, 2020·0 cites·6 claims
- 1526US8843870B2Method of reducing current leakage in a device and a device thereby formedSCATCHARD BRUCE·Filed 2012·Granted Sep 23, 2014·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →