Coupling circuit for preventing gate junction breakdown of flash memories

Abstract

The present invention discloses an NMOS coupling circuit for preventing gate junction breakdown of a flash memory. The present invention adds at least one isolating stage between a conducting stage and a high voltage HV of the prior coupling circuit, and the addition generates a benefit that the voltage difference of the high voltage HV is burdened by both the conducting stage and the isolating stage of the coupling circuit. In other words, the voltage difference in the gate junction of the conducting stage will be reduced, and the probability of punching through a transistor will also be reduced. For reducing the effect of an instant voltage difference when the high voltage HV is enabled, the present invention electrically connects one end of a diode to the gate of the isolating stage, and electrically connects another end of the diode to a lower power source VDD. Therefore, the magnitude of the VDD will be reduced from the instant voltage difference to protect the isolating stage from damaging when the high voltage HV is enabled.

What is claimed is:  
     
       1. A coupling circuit for preventing gate junction breakdown of a flash memory, comprising: 
       a high voltage;  
       a conducting stage for generating a power source of a rear-stage flash memory block;  
       a transistor enabled when the high voltage occurs; and  
       at least one isolating stage situated between the high voltage and the conducting stage for reducing a voltage difference of gate junctions of the conducting stage.  
     
     
       2. The coupling circuit of  claim 1 , wherein a gate terminal of the isolating stage is further connected to a diode whose one end is connected to a low voltage acting as a second power source of the flash memory block. 
     
     
       3. The coupling circuit of  claim 1 , wherein a gate terminal of is the isolating stage is further connected to the high voltage through a coupling capacitor. 
     
     
       4. The coupling circuit of  claim 1 , wherein a gate terminal of the isolating stage is further connected to a discharge path enabled when the high voltage is disabled. 
     
     
       5. The coupling circuit of  claim 4 , wherein the discharge path comprises at least one transistor. 
     
     
       6. A flash memory circuit, comprising: 
       a decoding circuit;  
       at least one coupling circuit including a high voltage enabled when the decoding circuit does not select the coupling circuit, a conducting stage and a transistor enabled when the high voltage occurs, wherein at least one isolating stage is added between the high voltage and the conducting stage for reducing a voltage difference of gate junctions of the conducting stage; and  
       at least one flash memory block utilizing the high voltage as a power source.  
     
     
       7. The flash memory circuit of  claim 6 , wherein the gate of the isolating stage is further connected to a diode whose one end is connected to a low voltage acting as a second power source of the flash memory block. 
     
     
       8. The flash memory circuit of  claim 6 , wherein the gate terminal of the isolating stage is further connected to the high voltage through a coupling capacitor. 
     
     
       9. The flash memory circuit of  claim 6 , wherein the gate terminal of the isolating stage is further connected to a discharge path enabled when the high voltage is disabled. 
     
     
       10. The flash memory circuit of  claim 9 , wherein the discharge path is formed by at least one transistor.