Non-volatile semiconductor memory device capable of suppressing writing and erasure failure rate

Abstract

There is provided a non-volatile semiconductor device having a memory cell in which a threshold value voltage changes in accordance with the application of the writing pulse having a predetermined width and voltage with respect to word lines and bit lines and data depending upon the threshold value voltage is written, wherein writing failure is generated in the first time data writing operation, and a writing condition is set for suppressing the writing condition is set which is capable of suppressing the writing failure rate than the case of the first time writing operation when the writing operation is re-executed.

What is claimed is:  
     
       1. A non-volatile semiconductor device having a memory cell in which a threshold value voltage changes and the data corresponding to the threshold value voltage are written in response to application of the writing pulse having a predetermined width and voltage to word lines and bit lines, the device executing a verify operation for judging the data from the threshold value voltage every application of the writing pulse in the data writing operation, characterized in that: 
       a rewriting condition is changed to a predetermined condition different from a first-time writing condition for suppressing the writing failure rate when the writing failure is generated in the first-time writing operation and the writing operation is re-executed.  
     
     
       2. The non-volatile semiconductor device according to  claim 1 , wherein the initial value of the writing pulse width is set to a level smaller than the value at the first-time writing operation when the writing operation is re-executed. 
     
     
       3. The non-volatile semiconductor device according to  claim 1 , wherein an increase rate of the writing pulse width is set to a smaller level than the first-time writing operation when the writing operation is re-executed. 
     
     
       4. The non-volatile semiconductor device according to  claim 1 , wherein the writing pulse width is set to an equal width with respect to a predetermined number of writing pulses after the start of the writing pulse when the writing operation is re-executed. 
     
     
       5. The non-volatile semiconductor device according to  claim 1 , the writing pulse voltage is set to a smaller level than the first-time writing operation when the writing operation is re-executed. 
     
     
       6. The non-volatile semiconductor device according to  claim 1 , wherein the reference scope of the threshold value used at the time of the verify is set to a level higher than that of the first-time writing operation when the writing operation is re-executed. 
     
     
       7. The non-volatile semiconductor device according to  claim 6 , wherein a voltage level which forms an upper limit of the reference scope of the threshold value voltage is set to a level higher than that of the first-time writing operation. 
     
     
       8. The non-volatile semiconductor device according to  claim 6 , wherein a voltage level which forms a lower limit of the reference scope of the threshold value voltage is set to a level lower than that of the first-time writing operation. 
     
     
       9. The non-volatile semiconductor memory device according to  claim 1 , wherein the corresponding relation between the data to be written and the threshold value voltage of the memory cell is changed when the writing operation is re-executed. 
     
     
       10. The non-volatile semiconductor memory device according to  claim 1 , wherein the corresponding relation between a memory cell in which data is written and the Y-address of the data is changed when the writing operation is re-executed. 
     
     
       11. The non-volatile semiconductor memory device according to  claim 1 , wherein the non-volatile semiconductor device is constituted in such a manner that a write back pulse having a predetermined width and voltage is applied to set the threshold value voltage to a predetermined value or more in the case where the threshold value voltage of the memory cell becomes less than the predetermined value voltage in the data erasure operation, and 
       wherein the writing condition is set which is capable of suppressing the write-back failure rate than the case of the first time erasure operation in the same manner that the writing condition can suppress the write failure rate than the first time writing operation, when the write-back failure is generated in the first time data erasure operation and the erasure operation is re-executed.