P
US6403496B2ExpiredUtilityPatentIndex 48

Method for forming shallow trench isolations

Assignee: WINDBOND ELECTRONICS CORPPriority: Sep 17, 1998Filed: Jan 5, 2001Granted: Jun 11, 2002
Est. expirySep 17, 2018(expired)· nominal 20-yr term from priority
Inventors:TIEN YU-CHUNG
H10W 10/014H10W 10/0145H10W 10/17
48
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Claims

Abstract

A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A method for forming planar shallow trench isolations in a wafer substrate having a silicon dioxide insulating layer disposed over the substrate and a silicon nitride layer disposed over the silicon dioxide insulating layer to form a substrate-insulator-silicon nitride stack, a surface of the substrate-insulator-silicon nitride stack being planar and having a plurality of trenches filled with silicon dioxide, comprising the steps of: 
       anisotropically etching the silicon dioxide layer to produce in the trenches silicon dioxide having sidewalls contiguous with the silicon nitride layer; and  
       isotropically etching to remove said silicon dioxide sidewalls such that the silicon dioxide in the trenches is planar with the silicon dioxide insulating layer.  
     
     
       2. The method as claimed in  claim 1  wherein said step of isotropically etching comprises a step of performing a buffered oxide etch. 
     
     
       3. The method as claimed in  claim 1  wherein said step of anisotropically etching comprises a step of etching with faster etch rate at the edge of the wafer.

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