Integrated circuit having a self-test device and method for producing the integrated circuit

Abstract

An integrated circuit incorporating a self-test device and a method for producing a self-testing integrated circuit. The integrated circuit has a program memory with at least one external terminal for loading external test programs. The integrated circuit has a self-test device connected to the program memory, the self-test device executing program commands of a test program loaded into the program memory, the program commands succeeding one another in address terms, for carrying out a self-test of the circuit. The self-test device has an interrupt signal input, through which the self-test device interrupts the test program that is currently being executed by not executing the respective succeeding program command in address terms. Rather, it executes a program jump within the test program, the program jump being triggered by the interrupt signal.

We claim:  
     
       1. An integrated circuit, comprising: 
       at least one external terminal;  
       a program memory connected to said at least one external terminal for loading external test programs into said program memory; and  
       a self-test device connected to said program memory and having an input for an interrupt signal, said self-test device executing program commands of the external test program loaded into said program memory to carry out a self-test of the integrated circuit, the program commands succeeding one another in address terms,  
       said self-test device, upon receiving the interrupt signal, interrupting an execution of the external test program by executing a program jump in address terms within the external test program instead of executing the respective succeeding program command of the external test program.  
     
     
       2. The integrated circuit according to  claim 1 , wherein said self-test device is a dynamic memory circuit having memory cells and program commands, said interrupt signal triggers a program jump to said program commands and execution of said program commands causes said self-test device to carry out a refresh of said memory cells. 
     
     
       3. The integrated circuit according to  claim 1 , including a time measuring device for generating said interrupt signal. 
     
     
       4. The integrated circuit according to  claim 1 , including a second external terminal for supplying said interrupt signal, said interrupt signal originating from outside the integrated circuit. 
     
     
       5. A method of producing a self-testing integrated circuit, the method which comprises: 
       providing a self-test device, a program memory and an external terminal;  
       connecting the self-test device to the program memory;  
       connecting the program memory to the external terminal;  
       loading external test programs having program commands into the program memory through the external terminal;  
       running the external test program and executing the program commands to carry out a self-test of the integrated circuit, the program commands succeeding one another in address terms;  
       generating an interrupt signal and inputting the interrupt signal into the self-test device; and  
       interrupting execution of the external test program being executed by the self-test device by executing a program jump in address terms within the external test program instead of executing the respective succeeding program command of the external test program, the program jump being triggered by the interrupt signal.  
     
     
       6. The method according to  claim 5 , which comprises subsequently executing the respective succeeding program command of the external test program after the program commands to carry out a self-test of the integrated circuit are complete. 
     
     
       7. The method according to  claim 5 , which comprises providing a dynamic memory circuit having memory cells, the step of executing the program commands comprising triggering a program jump to program commands that execute a refresh of the memory cells. 
     
     
       8. The method according to  claim 5 , wherein the step of generating the interrupt signal comprises generating the interrupt signal by a time measuring device. 
     
     
       9. The method according to  claim 5 , which comprises providing a further external terminal and feeding the interrupt signal from outside the integrated circuit through the further external terminal.