Structure and method for field emitter tips

Abstract

Improved methods and structures are provided for an array of vertical geometries which may be used as emitter tips, as a self aligned gate structure surrounding field emitter tips, or as part of a flat panel display. The present invention offers controlled size in emitter tip formation under a more streamlined process. The present invention further provides a more efficient method to control the gate to emitter tip proximity in field emission devices. The novel method of the present invention includes implanting a dopant in a patterned manner into the silicon substrate and anodizing the silicon substrate in a controlled manner causing a more heavily doped region in the silicon substrate to form a porous silicon region. Controlling the anodization of the silicon substrate further regulates and defines the shape to less heavily doped regions in the silicon substrate which form vertical geometries that can be used as emitter tips. One method of the present invention provides a self-aligned gate structure around emitter tips. Another method includes forming a field emission device. The present invention includes a novel field emitter array, a self aligned gate structure, a field emission device, and a display device all formed according to the methods provided in this application.

What is claimed is:  
     
       1. A method for forming vertical geometries on a silicon substrate, comprising: 
       implanting a dopant in a patterned manner into the silicon substrate, wherein implanting a dopant in a patterned manner includes defining a more heavily doped region in the silicon substrate surrounding a number of less heavily doped regions;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region, wherein anodizing the silicon substrate includes anodizing the silicon substrate in a self limiting manner by maximizing a dopant density in the silicon substrate and minimizing a current density through the silicon substrate in an HF/isopropyl alcohol bath;  
       oxidizing the porous silicon region to form an oxidized porous silicon region; and  
       removing the oxidized porous silicon region.  
     
     
       2. The method of  claim 1 , wherein implanting a dopant in a patterned manner into the silicon substrate includes defining the number of less heavily doped regions in a pillar geometry. 
     
     
       3. The method of  claim 1 , wherein implanting a dopant in a patterned manner into the silicon substrate includes implanting a p-type dopant. 
     
     
       4. The method of  claim 1 , wherein implanting a dopant in a patterned manner into the silicon substrate includes implanting a p-type dopant in a patterned manner into the silicon substrate for a mean dopant distribution at approximately 2000 Angstroms. 
     
     
       5. The method of  claim 1 , wherein anodizing the silicon substrate includes reducing a volume of the number of less heavily doped regions. 
     
     
       6. A method for forming pillars of silicon, comprising: 
       forming a patterned mask on a silicon substrate, wherein forming the patterned mask includes defining a number of pillar regions;  
       implanting a dopant into the silicon substrate surrounding the number of pillar regions such that the silicon substrate has a more heavily doped region;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region, wherein anodizing the silicon substrate includes anodizing the silicon substrate in a self limiting manner by maximizing a dopant density in the silicon substrate and minimizing a current density through the silicon substrate in an HF/isopropyl alcohol bath;  
       oxidizing the porous silicon region to form an oxidized porous region; and  
       removing the oxidized porous region.  
     
     
       7. The method of  claim 6 , wherein removing the oxidized porous silicon region includes using a wet etch process to remove the oxidized porous silicon region. 
     
     
       8. The method of  claim 6 , wherein anodizing the silicon substrate includes placing the silicon substrate in an HF/isopropyl alcohol bath and sourcing the HF/isopropyl alcohol bath in a low current, high voltage process. 
     
     
       9. The method of  claim 6 , wherein anodizing the silicon substrate includes suspending the silicon substrate in an HF/isopropyl alcohol bath and sourcing a current through the HF/isopropyl alcohol bath by placing two separate electrodes in the HF/isopropyl alcohol bath. 
     
     
       10. The method of  claim 6 , wherein anodizing the silicon substrate includes suspending the silicon substrate in an HF/isopropyl alcohol bath along with multiple wafers in a batch process. 
     
     
       11. The method of  claim 6 , wherein anodizing the silicon substrate includes controlling the anodization period, wherein controlling the anodization period includes regulating a shape to the number of pillar regions. 
     
     
       12. The method of  claim 11 , wherein regulating a shape to the number of pillar regions includes defining the number of pillar regions in a conical shape. 
     
     
       13. A method for forming pillars of silicon, comprising: 
       forming a patterned mask on a silicon substrate, wherein the patterned mask defines a number of pillar regions;  
       implanting a dopant into the silicon substrate surrounding the number of pillar regions such that the silicon substrate has a more heavily doped region;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate includes reducing a size for the number of pillar regions underneath the patterned mask, and wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region;  
       oxidizing the porous silicon region to form an oxidized porous silicon region;  
       removing the oxidized porous silicon region;  
       forming an insulator layer surrounding the pillar region; and  
       forming a gate layer on the insulator layer.  
     
     
       14. The method of  claim 13 , wherein forming a patterned mask includes forming multiple islands of silicon nitride having circular geometries. 
     
     
       15. The method of  claim 14 , wherein forming multiple islands of silicon nitride having circular geometries includes controlling the width to height ratio of the multiple islands of silicon nitride in order to define a diameter for each of the number of pillar regions. 
     
     
       16. The method of  claim 13 , wherein implanting a dopant into the silicon substrate surrounding the number of pillar regions includes implanting a p-type dopant for a mean distribution at approximately 2000 Angstroms. 
     
     
       17. The method of  claim 16 , wherein the method further includes annealing the silicon substrate to create a uniform distribution of the dopant. 
     
     
       18. A method for forming an array of field emitter tips, comprising: 
       implanting a dopant in a patterned manner into a silicon substrate, wherein implanting a dopant in a patterned manner includes defining a more heavily doped region in the silicon substrate surrounding a number of less heavily doped emitter tip regions;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region, and wherein anodizing the silicon substrate includes further defining a shape for the number of less heavily doped emitter tip regions;  
       oxidizing the porous silicon region to form an oxidized porous silicon region;  
       removing the oxidized porous silicon region;  
       forming an insulator layer surrounding the emitter tip regions; and  
       forming a gate layer on the insulator layer.  
     
     
       19. The method of  claim 18 , wherein implanting a dopant in a patterned manner into the silicon substrate includes forming multiple islands of silicon nitride having circular geometries on the silicon substrate, wherein forming multiple islands of silicon nitride includes defining the number of less heavily doped emitter tip regions. 
     
     
       20. The method of  claim 18 , wherein implanting a dopant in a patterned manner into the silicon substrate includes defining the number of less heavily doped emitter tip regions in a pillar geometry. 
     
     
       21. The method of  claim 18 , wherein implanting a dopant in a patterned manner into the silicon substrate includes implanting a p-type dopant in a patterned manner into the silicon substrate for a mean dopant distribution at approximately 2000 Angstroms. 
     
     
       22. The method of  claim 18 , wherein anodizing the silicon substrate includes creating a textured surface on the number of less heavily doped emitter tip regions. 
     
     
       23. A method for forming a self-aligned gate structure around emitter tips, comprising: 
       forming a patterned mask on a silicon substrate, wherein forming the patterned mask includes defining a number of emitter tip regions;  
       implanting a dopant into the silicon substrate, wherein implanting a dopant into the silicon substrate includes defining a more heavily doped region in the silicon substrate surrounding the number of emitter tip regions;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region;  
       oxidizing the porous silicon region to form an oxidized region;  
       forming a gate layer over the oxidized region and the patterned mask, wherein forming a gate layer over the oxidized region and the patterned mask includes removing a portion of the oxidized region such that a top surface layer of the oxidized region is below a bottom surface of the patterned mask, and wherein removing a portion of the oxidized region includes etching the oxidized region back using a dry etch process.  
     
     
       24. The method of  claim 23 , wherein forming a patterned mask includes forming multiple islands of silicon nitride having circular geometries and controlling the width to height ratio of the multiple islands of silicon nitride in order to define the number of emitter tip regions. 
     
     
       25. The method of  claim 23 , wherein forming the gate layer over the oxidized region and the patterned mask includes first reducing the size of the patterned mask. 
     
     
       26. The method of  claim 25 , wherein reducing the size of the patterned mask includes using a dry etch process for reducing the size of the patterned mask. 
     
     
       27. A method for forming a self-aligned gate structure around emitter tips, comprising: 
       forming a patterned mask on a silicon substrate, wherein forming the patterned mask includes defining a number of emitter tip regions;  
       implanting a dopant into the silicon substrate, wherein implanting a dopant into the silicon substrate includes defining a more heavily doped region in the silicon substrate surrounding the number of emitter tip regions;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate includes further regulating a shape for the number of less heavily doped emitter tip regions, and wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region;  
       oxidizing the porous silicon region to form an oxidized region;  
       removing a portion of the oxidized region such that a top surface layer of the oxidized region is below a bottom surface of the patterned mask;  
       forming a gate layer over the oxidized region and the patterned mask, wherein forming the gate layer over the oxidized region and the patterned mask includes first reducing the size of the patterned mask, and wherein reducing the size of the patterned mask includes using a dry etch process for reducing the size of the patterned mask.  
     
     
       28. The method of  claim 27 , wherein forming a gate layer on the oxidized region and the patterned mask includes forming a refractory metal gate layer. 
     
     
       29. The method of  claim 27 , wherein forming a gate layer on the oxidized region and the patterned mask includes sputtering a gate layer over the oxidized region and the patterned mask. 
     
     
       30. The method of  claim 27 , wherein the method further includes removing the gate layer from a top surface of the patterned mask. 
     
     
       31. The method of  claim 30 , wherein the method further includes removing the patterned mask. 
     
     
       32. The method of  claim 31 , wherein the method further includes etching out a portion of the oxidized region surrounding the number of emitter tip regions. 
     
     
       33. The method of  claim 36 , wherein etching out a portion of the oxidized region surrounding the number of emitter tip regions includes performing a selective dry etch. 
     
     
       34. A method for forming a field emission device, comprising: 
       implanting a dopant in a patterned manner into a silicon substrate, wherein implanting a dopant in a patterned manner includes defining a more heavily doped region in the silicon substrate surrounding a number of less heavily doped emitter tip regions;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate includes controlling the anodization period, wherein controlling the anodization period includes regulating a shape on each of the number of emitter tip regions, and wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region;  
       oxidizing the porous silicon region to form an oxidized porous silicon region;  
       forming a patterned gate layer over the oxidized porous silicon region, wherein forming a patterned gate layer on the oxidized porous silicon region includes depositing a doped polysilicon layer.  
     
     
       35. The method of  claim 34 , wherein regulating the shape on each of the number of emitter tip regions includes forming the number of emitter tip regions in a conical shape. 
     
     
       36. The method of  claim 34 , wherein forming a patterned gate layer over the oxidized porous silicon region includes etching back a portion of the oxidized porous silicon region. 
     
     
       37. A method of forming a field emission device, comprising: 
       forming a patterned mask on a silicon substrate, wherein forming the patterned mask includes defining a number of emitter tip regions;  
       implanting a dopant into the silicon substrate, wherein implanting a dopant into the silicon substrate includes defining a more heavily doped region in the silicon substrate surrounding the number of emitter tip regions;  
       anodizing the silicon substrate, wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region;  
       oxidizing the porous silicon region to form an oxidized porous silicon region;  
       removing a portion of the oxidized porous silicon region such that a top surface of the oxidized porous silicon region is below a bottom surface of the patterned mask; and  
       forming a gate layer over the oxidized porous silicon region and the patterned mask, wherein forming a gate layer includes;  
       forming a conductive layer on the oxidized porous silicon region and the patterned mask, wherein forming a conductive layer on the oxidized porous silicon region and the patterned mask includes depositing a doped polysilicon layer;  
       removing a portion of the conductive layer to expose the patterned mask;  
       removing the patterned mask; and  
       removing a portion of the oxidized porous silicon region surrounding the number of emitter tip regions.  
     
     
       38. The method of  claim 37 , wherein forming a patterned mask defining a number of emitter tip regions includes forming multiple islands of silicon nitride having circular geometries. 
     
     
       39. The method of  claim 37 , wherein forming a conductive layer on the oxidized porous silicon region and the patterned mask includes sputtering a conductive layer onto the oxidized porous silicon region.