PD-SOI substrate with suppressed floating body effect and method for its fabrication

Abstract

A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

What is claimed as new and desired to be protected by Letters Patent of the United States is:  
     
       1. A SOI structure comprising: 
       a silicon/germanium layer formed between a first silicon layer and a second silicon layer, said silicon/germanium layer being in contact with said first and second silicon layers, said silicon/germanium layer comprising approximately 0.5 to 6% germanium; and  
       an oxide layer formed over a semiconductor substrate, said oxide layer being in contact with said second silicon layer.  
     
     
       2. The SOI structure of  claim 1  , wherein said silicon/germanium layer is an epitaxial silicon/germanium layer. 
     
     
       3. The SOI structure of  claim 1 , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick. 
     
     
       4. The SOI structure of  claim 1 , wherein said silicon/germanium layer is approximately 200 Angstroms thick. 
     
     
       5. The SOI structure of  claim 1 , wherein said silicon/germanium layer comprises approximately 5% germanium. 
     
     
       6. The SOI structure of  claim 1 , wherein said first silicon layer is an epitaxial silicon layer. 
     
     
       7. The SOI structure of  claim 6 , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick. 
     
     
       8. The SOI structure of  claim 6 , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick. 
     
     
       9. The SOI structure of  claim 1 , wherein said second silicon layer is an epitaxial silicon layer. 
     
     
       10. The SOI structure of  claim 9 , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick. 
     
     
       11. The SOI structure of  claim 9 , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick. 
     
     
       12. The SOI structure of  claim 1 , wherein said oxide layer is approximately 1 micron thick. 
     
     
       13. The SOI structure of  claim 1 , wherein said semiconductor substrate is a silicon substrate. 
     
     
       14. The SOI structure of  claim 1 , wherein said semiconductor substrate is a silicon-on-saphire substrate. 
     
     
       15. The SOI structure of  claim 1 , wherein said semiconductor substrate is a germanium substrate. 
     
     
       16. The SOI structure of  claim 1 , wherein said semiconductor substrate is a gallium-arsenide substrate. 
     
     
       17. The SOI structure of  claim 1 , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides. 
     
     
       18. The SOI structure of  claim 15 , wherein said oxide layer is formed of silicon dioxide. 
     
     
       19. A memory cell, comprising: 
       a SOI substrate comprising a silicon/germanium layer formed between a first silicon layer and a second silicon layer, and an oxide layer bonded to said second silicon layer, said oxide layer being formed on a semiconductor substrate, said silicon/germanium layer comprising approximately 0.5 to 6% germanium; and  
       a transistor including a gate fabricated on said SOI substrate and including source and drain regions fabricated adjacent to said gate.  
     
     
       20. The memory cell of  claim 19 , wherein said silicon/germanium layer is an epitaxial silicon/germanium layer. 
     
     
       21. The memory cell of  claim 19 , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick. 
     
     
       22. The memory cell of  claim 19 , wherein said silicon/germanium layer is approximately 200 Angstroms thick. 
     
     
       23. The memory cell of  claim 19 , wherein said silicon/germanium layer comprises approximately 5% germanium. 
     
     
       24. The memory cell of  claim 19 , wherein said first silicon layer is an epitaxial silicon layer. 
     
     
       25. The memory cell of  claim 24 , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick. 
     
     
       26. The memory cell of  claim 24 , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick. 
     
     
       27. The memory cell of  claim 19 , wherein said second silicon layer is an epitaxial silicon layer. 
     
     
       28. The memory cell of  claim 27 , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick. 
     
     
       29. The memory cell of  claim 27 , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick. 
     
     
       30. The memory cell of  claim 19 , wherein said oxide layer is approximately 1 micron thick. 
     
     
       31. The memory cell of  claim 19 , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides. 
     
     
       32. A processor system comprising: 
       a processor; and  
       an integrated circuit coupled to said processor and comprising a SOI substrate, said SOI substrate comprising a silicon/germanium layer formed between a first epitaxial silicon layer and a second epitaxial silicon layer, and an oxide layer bonded to said second epitaxial silicon layer, said oxide layer being formed on a semiconductor substrate, said silicon/germanium layer comprising approximately 0.5 to 6% germanium.  
     
     
       33. The processor system of  claim 32 , wherein said silicon/germanium layer is an epitaxially grown layer. 
     
     
       34. The processor system of  claim 32 , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick. 
     
     
       35. The processor system of  claim 32 , wherein said silicon/germanium layer is approximately 200 Angstroms thick. 
     
     
       36. The processor system of  claim 32 , wherein said silicon/germanium layer comprises approximately 5% germanium. 
     
     
       37. The processor system of  claim 32 , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick. 
     
     
       38. The processor system of  claim 32 , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick. 
     
     
       39. The processor system of  claim 32 , wherein said oxide layer is approximately 1 micron thick. 
     
     
       40. The processor system of  claim 32 , wherein said semiconductor substrate is a silicon substrate. 
     
     
       41. The processor system of  claim 32 , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides. 
     
     
       42. The processor system of  claim 32 , wherein said integrated circuit is a memory device. 
     
     
       43. The processor system of  claim 42 , wherein said memory device is a random access memory device. 
     
     
       44. A SOI structure comprising: 
       a first silicon/germanium layer formed between a first silicon layer and a second silicon layer, said first silicon/germanium layer being in contact with said first and second silicon layers, said first silicon/germanium layer comprising approximately 0.5 to 6% germanium;  
       a second silicon/germanium layer formed between a third silicon layer and said second silicon layer, said second silicon/germanium layer being in contact with said second and third silicon layers; and  
       an oxide layer formed over a semiconductor substrate, said oxide layer being in contact with said third silicon layer.  
     
     
       45. The SOI structure of  claim 44 , wherein said first and second silicon/germanium layers are epitaxially grown layers. 
     
     
       46. The SOI structure of  claim 44 , wherein said first and second silicon/germanium layers are approximately 100 to 300 Angstroms thick. 
     
     
       47. The SOI structure of  claim 44 , wherein said first and second silicon/germanium layers are approximately 200 Angstroms thick. 
     
     
       48. The SOI structure of  claim 44 , wherein said first and second silicon/germanium layers comprise approximately 5% germanium. 
     
     
       49. The SOI structure of  claim 44 , wherein said first silicon layer is an epitaxial silicon layer. 
     
     
       50. The SOI structure of  claim 44 , wherein said first silicon layer is approximately 500 to 3,000 Angstroms thick. 
     
     
       51. The SOI structure of  claim 44 , wherein said second silicon layer is an epitaxial silicon layer. 
     
     
       52. The SOI structure of  claim 44 , wherein said second silicon layer is approximately 300 to 1,500 Angstroms thick. 
     
     
       53. The SOI structure of  claim 44 , wherein said third silicon layer is an epitaxial silicon layer. 
     
     
       54. The SOI structure of  claim 44 , wherein said third silicon layer is approximately 300 to 1,500 Angstroms thick. 
     
     
       55. The SOI structure of  claim 44 , wherein said oxide layer is approximately 1 micron thick.