Electrostatic discharge protection apparatus

Abstract

An electrostatic discharge protection apparatus. A drain region is formed under a pad. A gate is formed at a periphery of the pad, while a source region is formed at a periphery of the gate. Another kind of electrostatic discharge protection apparatus is also presented with a drain region formed under a pad. More than one gate is formed at a periphery of the pad, and each gate is surrounded with a source region. Further in the invention, an electrostatic discharge protection apparatus is further presented with a P-type and N-type drain region located under a pad. A first gate and a second gate are formed at a periphery of pad corresponding thereto, respectively. In the above manners, the layout of the electrostatic discharge protection can be highly packed, that is, the occupied area is greatly reduced.

What is claimed is:  
     
       1. An electrostatic discharge protection apparatus, comprising: 
       a pad;  
       a drain region, under the pad;  
       a gate, located at a periphery of the pad, wherein the gate surrounds the pad; and  
       a source region, at a periphery of the gate, wherein the source region surrounds the gate.  
     
     
       2. The protection apparatus according to  claim 1 , wherein the gate comprises a polysilicon gate. 
     
     
       3. The protection apparatus according to  claim 1 , wherein the drain region, the gate and the source region together form either a PMOS transistor or an NMOS transistor. 
     
     
       4. An electrostatic discharge protection apparatus, comprising: 
       a pad;  
       a drain region, covered by the pad;  
       a plurality of gates, located around a periphery of the pad; and  
       a plurality of source regions, wherein each of the source regions with respect to the gates is located at an outer periphery of the gates.  
     
     
       5. The protection apparatus according to  claim 4 , wherein the gates comprise polysilicon gates. 
     
     
       6. The protection apparatus according to  claim 4 , wherein the drain region, one of the gates and one of the source regions surrounding the gates together form either a PMOS transistor or an NMOS transistor. 
     
     
       7. An electrostatic discharge protection, comprising: 
       a pad, divided into a first portion and a second portion;  
       a heavily doped P-type drain region, located under the first portion of the pad;  
       a heavily doped N-type drain region, located under the second portion of the pad;  
       a first gate, around an outer periphery of the first portion of the pad;  
       a second gate, around an outer periphery of the second portion of the pad;  
       a heavily doped P-type source region, around an outer periphery of the first gate; and  
       a heavily doped N-type source region, around an outer periphery of the second gate.  
     
     
       8. The protection apparatus according to  claim 7 , wherein the first and second gates comprise polysilicon gates. 
     
     
       9. The protection apparatus according to  claim 1 , wherein the drain region has an area substantially equal to an area of the pad. 
     
     
       10. The protection apparatus according to  claim 4 , wherein the drain region has an area substantially equal to an area of the pad. 
     
     
       11. The protection apparatus according to  claim 7 , wherein an area of the heavily doped P-type drain region is about equal to an area of the first portion of the pad, and an area of the heavily doped N-type drain region is about equal to an area of the second portion of the pad.