Interconnect line selectively isolated from an underlying contact plug

Abstract

The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed as initially partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration. In subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.

What is claimed as new and desired to be protected by Letters Patent of the United States is:  
     
       1. A method of forming a semiconductor device, comprising: 
       forming a first contact stud and a second contact stud, each connected to a respective active area of a semiconductor substrate;  
       forming a first silicide cap on top of said first contact stud and a second suicide cap on top of said second contact stud;  
       forming an interconnect line above said first contact stud and in contact with said first silicide cap, and at least in partial contact with said second silicide cap; and  
       isolating said interconnect line from said second contact stud by selectively removing said second silicide cap from over said second contact stud and providing an insulator between said interconnect line and said second contact stud.  
     
     
       2. A method as in  claim 1  wherein said isolating comprises: 
       forming an insulating layer over and around said interconnect line;  
       forming a contact hole through said insulating layer to remove said second silicide cap; and  
       forming an insulating sidewall inside said contact hole which insulates said second contact stud from said interconnect line.  
     
     
       3. A method as in  claim 2  further comprising forming a conductive plug within said contact hole and within said insulating sidewalls, in electrical contact with said second contact stud. 
     
     
       4. The method of  claim 1  wherein said first contact stud is provided between a pair of wordline gates of a memory device. 
     
     
       5. The method of  claim 1  wherein said second contact stud is provided between a wordline gate and an isolation gate of a memory device. 
     
     
       6. The method of  claim 1  wherein said first and second contact studs are formed of polysilicon. 
     
     
       7. The method of  claim 1  wherein said first and second contact studs are formed simultaneously. 
     
     
       8. The method of  claim 1  wherein said interconnect line is a bit line of a memory cell. 
     
     
       9. The method of  claim 1  further comprising forming a capacitor in electrical contact with said second contact stud. 
     
     
       10. The method of  claim 9  wherein said capacitor includes a bottom electrode which is formed simultaneously with a conductive plug in electrical contact with said second contact stud. 
     
     
       11. The method of  claim 1  wherein said selective removing of said second silicide cap includes wet etching. 
     
     
       12. The method of  claim 2  wherein said insulating sidewall is formed of a layer of at least one of SiO 2  and Si 3 N 4 . 
     
     
       13. The method of  claim 3  wherein said conductive plug is formed of a material selected from the group consisting of polysilicon and a metal-based material. 
     
     
       14. The method of  claim 13  wherein said metal-based material is formed of one or more materials selected from the group consisting of W, TiN, Pt, Ru, Al, another metal selected from Groups IVB, VB, BIB, BIII, IB, IIB, or IIIA of the Periodic Table, alloys of the preceding, oxides of the preceding, carbides of the preceding, borides of the preceding, and combinations of the preceding. 
     
     
       15. A method of forming at least a portion of a DRAM cell array, said method comprising: 
       forming at least one transistor gate and associated source and drain regions on a semiconductor substrate;  
       forming a first contact stud and a second contact stud, each connected to a respective one of said source and drain regions;  
       forming a first silicide cap on top of said first contact stud and a second silicide cap on top of said second contact stud;  
       forming an interconnect line above said first contact stud and in contact with said first silicide cap, and at least in partial contact with said second suicide cap; and  
       selectively removing said second suicide cap from above said second contact stud.  
     
     
       16. A method as in  claim 15 , further comprising forming an insulating sidewall inside a contact hole to said second contact stud, wherein said contact hole is through an insulating layer which is formed over and around said interconnect line. 
     
     
       17. A method as in  claim 16 , further comprising forming a conductive plug within said contact hole and within said insulating sidewall and in electrical contact with said second contact stud. 
     
     
       18. The method of  claim 15  wherein said transistor gate is a wordline gate. 
     
     
       19. The method of  claim 15  wherein said first and second contact studs are formed simultaneously by etching holes to said source and drain regions through an insulating layer formed over said transistor gate, and depositing polysilicon within said holes. 
     
     
       20. The method of  claim 15  wherein said first and second silicide caps are formed utilizing a selective deposition method. 
     
     
       21. The method of  claim 15  further comprising having a capacitor in electrical contact with said second contact stud. 
     
     
       22. The method of  claim 21  wherein said capacitor includes a bottom electrode which is formed simultaneously with a conductive plug in electrical contact with said second contact stud. 
     
     
       23. The method of  claim 15  wherein said interconnect line is a bit line. 
     
     
       24. The method of  claim 15  wherein said selective removing of said second silicide cap includes wet etching. 
     
     
       25. The method of  claim 16  wherein said insulating sidewall is formed by depositing a thin dielectric layer within said contact hole and etching said thin dielectric layer. 
     
     
       26. The method of  claim 25  wherein said thin dielectric layer comprises a material selected from at least one of SiO 2  and Si 3 N 4 . 
     
     
       27. The method of  claim 17  wherein said conductive plug is formed of a material selected from the group consisting of polysilicon and a metal-based material. 
     
     
       28. The method of  claim 27  wherein said metal-based material is formed of one or more materials selected from the group consisting of W, TiN, Pt, Ru, Al, another metal selected from Groups IVB, VB, BIB, BIII, IB, IIB, or IIIA of the Periodic Table, alloys of the preceding, oxides of the preceding, carbides of the preceding, borides of the preceding, and combinations of the preceding. 
     
     
       29. A method of forming a semiconductor device, comprising: 
       forming a least one gate structure and associated active areas on a semiconductor substrate;  
       forming a first insulating layer over said gate structure and said substrate;  
       etching at least a first and a second contact hole through said first insulating layer to respective one of said active area;  
       forming at least a first and a second contact stud within said first and second contact holes, respectively;  
       forming at least a first and a second silicide cap on said first and second contact studs, respectively;  
       forming at least one interconnect line over said contact studs and suicide caps, wherein said interconnect line is in contact with said first silicide cap and at least in partial contact with said second silicide cap;  
       forming a second insulating layer over and around said interconnect line;  
       etching at least one third contact hole in said second insulating layer to said second silicide cap;  
       removing said second silicide cap within said third contact hole from the top of said second contact stud;  
       forming a third insulating layer at least within said third contact hole to insulate said interconnect line from said second contact stud;  
       etching said third insulating layer to said second contact stud to form insulating sidewalls within said third contact hole; and  
       forming a conductive plug in contact with said second contact stud and within said insulating sidewalls.  
     
     
       30. The method of  claim 29  wherein said first and second contact studs are formed simultaneously using polysilicon. 
     
     
       31. The method of  claim 29  further comprising forming a capacitor in electrical contact with said second contact stud, and wherein said first contact stud is provided for connecting a bit line of said memory device to said respective one of said active areas. 
     
     
       32. The method of  claim 31  wherein said capacitor includes a bottom electrode which is formed simultaneously with said conductive plug. 
     
     
       33. The method of  claim 29  wherein said selective etching uses a wet etch. 
     
     
       34. The method of  claim 29  wherein said thin dielectric layer comprises a material selected from at least one of SiO 2  and Si 3 N 4 . 
     
     
       35. The method of  claim 29  wherein said conductive plug is formed of a material selected from the group consisting of polysilicon or a metal selected from the group consisting of W, TiN, Pt, Ru, Al, another metal selected from Groups IVB, VB, BIB, BIII, IB, IIB, or IIIA of the PEriodic Table, alloys of the preceding, oxides of the preceding, carbides of the preceding, borides of the preceding, and combinations of the preceding. 
     
     
       36. A method of isolating an interconnect line from a partially underlying contact of a DRAM memory cell, said method comprising: 
       forming a first silicide cap on a first contact stud over a first active area on a semiconductor substrate and a second silicide cap on a second contact stud over a second active area on said semiconductor substrate;  
       forming an interconnect line over said first silicide cap and at least in partial contact with said second silicide cap;  
       etching a contact hole to said second silicide cap, through an insulating layer formed over and around said interconnect line, and selectively etching said second suicide cap from over said second contact stud;  
       forming insulating sidewalls in said contact hole to insulate said second contact stud from said interconnect line; and  
       forming a conductive plug electrically connected to said second contact stud and within said insulating sidewalls.  
     
     
       37. A method of isolating an interconnect line from a partially underlying contact of a DRAM memory cell, said method comprising: 
       forming a first contact stud over a first active area on a semiconductor substrate and a second contact stud over a second active area on said semiconductor substrate;  
       forming an interconnect line over said first contact stud and at least in partial contact with said second contact stud;  
       etching a contact hole to said second contact stud, through an insulating layer formed over and around said interconnect line, and selectively etching a portion of said second contact stud to remove any direct electrical contact with said interconnect line;  
       forming insulating sidewalls in said contact hole to insulate said second contact stud from said interconnect line; and  
       forming a conductive plug electrically connected to said second contact stud and within said insulating sidewalls.  
     
     
       38. The method of  claim 37  wherein said first contact stud is provided between a pair of wordline gates. 
     
     
       39. The method of  claim 37  wherein said second contact stud is provided between a wordline gate and an isolation gate. 
     
     
       40. The method of  claim 37  wherein said first and second contact studs are formed of polysilicon. 
     
     
       41. The method of  claim 37  wherein said first and second contact studs are formed simultaneously. 
     
     
       42. The method of  claim 37  wherein said interconnect line is a bit line. 
     
     
       43. The method of  claim 37  further comprising having a capacitor in electrical contact with said second contact stud. 
     
     
       44. The method of  claim 43  wherein said capacitor includes a bottom electrode which is formed simultaneously with said conductive plug. 
     
     
       45. The method of  claim 37  wherein said selective etching of said portion of said second contact stud includes wet etching. 
     
     
       46. The method of  claim 37  wherein said insulating sidewall is formed of a layer of at least one of SiO 2  and Si 3 N 4 . 
     
     
       47. The method of  claim 37  wherein said conductive plug is formed of a material selected from the group consisting of polysilicon and a metal-based material. 
     
     
       48. The method of  claim 47  wherein said metal-based material is formed of one or more materials selected from the group consisting of W, TiN, Pt, Ru, Al, another metal selected from Groups IVB, VB, BIB, BIII, IB, IIB, or IIIA of the PEriodic Table, alloys of the preceding, oxides of the preceding, carbides of the preceding, borides of the preceding, and combinations of the preceding.