Dual rail power supply sequence tolerant off-chip driver

Abstract

The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

What is claimed is:  
     
       1. A semiconductor chip, comprising: 
       a first plurality of circuits connected to a first voltage contact having a first voltage potential, and to a ground contact;  
       a second plurality of circuits connected to a second voltage contact having a second voltage potential, and to said ground contact;  
       a detection circuit connected to said first voltage contact, said second voltage contact, and said ground contact, and having an output node;  
       said detection circuit adapted to operate by detecting the loss of voltage potential at said first voltage contact;  
       said detection circuit adapted to pull said output node to said second voltage potential when said first voltage potential and said second voltage potential are both present; and  
       said detection circuit adapted to pull said output node to ground potential when said first voltage potential is not present.  
     
     
       2. The semiconductor chip of  claim 1 , wherein the first and second plurality of circuits are implemented with complementary metal oxide semiconductor (CMOS) transistors. 
     
     
       3. The semiconductor chip of  claim 1 , wherein the first voltage contact is at a nominal voltage of about 2.5 volts. 
     
     
       4. The semiconductor chip of  claim 1 , wherein the second voltage contact is at a nominal voltage of about 3.3 volts. 
     
     
       5. The semiconductor chip of  claim 2 , wherein the detection circuit comprises: 
       an inverting levels translator circuit; and  
       a select circuit.  
     
     
       6. The semiconductor chip of  claim 5 , wherein said select circuit comprises: 
       a first transistor and a second transistor;  
       the first transistor is an NFET with its source connected to ground, its drain connected to the output node, and its gate connected to the output of said inverting levels translator circuit; and  
       the second transistor is a PFET with its drain connected to said second voltage potential, its source connected to the output node, and its gate connected to the output of the inverting levels translator circuit.  
     
     
       7. A semiconductor chip, comprising: 
       a first plurality of circuits connected to a first voltage contact having a first voltage potential, and to a ground contact, wherein said first plurality of circuits are implemented with complementary metal oxide semiconductor (CMOS) transistors;  
       a second plurality of circuits connected to a second voltage contact having a second voltage potential, and to said ground contact, wherein said second plurality of circuits are implemented with complementary metal oxide semiconductor (CMOS) transistors;  
       a detection circuit connected to said first voltage contact, said second voltage contact, and said ground contact, and having an output node;  
       said detection circuit adapted to operate by detecting the loss of voltage potential at said first voltage contact;  
       said detection circuit adapted to pull said output node to said second voltage potential when said first voltage potential and said second voltage potential are both present; and  
       said detection circuit adapted to pull said output node to ground potential when said first voltage potential is not present;  
       said detection circuit comprising an inverting levels translator circuit and a select circuit, wherein said inverting levels translator circuit further comprises:  
       first, second and third NFET transistors;  
       first and second PFET transistors;  
       said first NFET transistor having its source connected said second voltage potential, its drain connected to the gate of the second NFET transistor, and its gate connected to the second voltage potential;  
       said second NFET transistor having its source connected to a second node, its drain connected to said first voltage potential, and its gate connected to the drain of said first NFET transistor;  
       said third NFET transistor having its drain connected to an output node of said inverting levels translator circuit, its source connected to ground potential, and its gate connected to said first voltage potential;  
       said first PFET transistor having its source connected to said second voltage potential, its drain connected to said second node, and its gate connected to said output node of said inverting levels translator circuit; and  
       said second PFET transistor having its source connected to said second voltage potential, its drain connected to said output node of said inverting levels translator circuit, and its gate connected to said second node.  
     
     
       8. A semiconductor interface circuit for translating lower voltage logic levels into higher voltage logic levels and vice versa, comprising: 
       a first voltage contact;  
       a second voltage contact;  
       a ground contact;  
       a detection circuit having an output node, and adapted to force said output node to ground potential, only when a second voltage source is connected to said second voltage contact and no voltage source is connected to said first voltage contact, wherein said detection circuit includes a sensing circuit, and wherein said sensing circuit monitors the voltage levels at the first and second voltage contacts; and  
       wherein the semiconductor interface circuit is adapted to enter a high impedance state when said output node is pulled to said ground potential at the ground contact.  
     
     
       9. The semiconductor interface circuit of  claim 8 , wherein said detection circuit further includes a bias circuit. 
     
     
       10. A method of protecting circuitry in a semiconductor chip, comprising: 
       providing a first plurality of circuits connected to a first voltage contact and a ground potential contact;  
       providing a second plurality of circuits connected to a second voltage contact and said ground potential contact;  
       providing a detection and bias circuit connected to said first voltage contact and said second voltage contact, and having an output node, said detection and bias circuit operating by forcing said output node to said ground potential contact only when a second voltage source is connected to said second voltage contact and no voltage source is detected at said first voltage contact; and  
       connecting at least one of said second plurality of circuits to said output node of said detection and bias circuit.  
     
     
       11. The method of  claim 10 , further comprising the step of: 
       adapting at least one of said second plurality of circuits to enter a high impedance state when said output node is pulled to said ground contact.  
     
     
       12. The method of  claim 10 , further comprising the step of providing an inverting levels translator circuit for monitoring the presence of a first voltage potential at the first voltage contact as part of the detection and bias circuit. 
     
     
       13. A two-supply input/output protection circuit comprising: 
       a driver input stage having a data input connected to a first levels translation apparatus and an enable input connected to a second levels translation apparatus, wherein each of said first and second levels translation apparatus has an output connected to an output of said input stage;  
       a detection stage having a pre-drive stage comprising a NAND gate and a NOR gate, said detection stage operationally connected to said output of said input stage;  
       an output stage operationally connected to an output of the pre-drive stage; and  
       a loss detection stage having an inverter stage and a voltage bias stage, said inverter stage operationally connected to said driver input stage, and said voltage bias stage operationally connected to said output stage.  
     
     
       14. The protection circuit of  claim 13 , said voltage bias stage further comprising: 
       a first transistor, said first transistor being a p-channel field effect transistor (PFET); and  
       a second transistor, said second transistor being an n-channel field effect transistor (NFET).  
     
     
       15. The protection circuit of  claim 14 , wherein the first transistor and the second transistor operationally form a select circuit. 
     
     
       16. The protection circuit of  claim 13  wherein the voltage bias stage comprises: 
       a PFET device with its drain connected to a first voltage potential, its source connected to an output, its gate connected to the output of said inverter stage; and  
       an NFET device with its source connected to ground potential, its gate connected to the gate of said PFET device, and its drain connected to said output.  
     
     
       17. The protection circuit of  claim 13 , wherein the output stage is switchable to a high impedance state. 
     
     
       18. A two-supply input/output protection circuit comprising: 
       a driver input stage having a data input connected to a first levels translation apparatus and an enable input connected to a second levels translation apparatus, wherein each of said first and second levels translation apparatus has an output connected to an output of said driver input stage;  
       a detection stage having a pre-drive stage comprising a NAND gate and a NOR gate, said detection stage operationally connected to said output of said driver input stage;  
       an output stage operationally connected to an output of the pre-drive stage;  
       a loss detection stage having an inverter stage and a voltage bias stage, said inverter stage operationally connected to said driver input stage, and said voltage bias stage operationally connected to said output stage; and  
       said inverter stage including an inverting levels translation circuit for monitoring the presence of a first voltage potential and a second voltage potential.