Inventor

CORREALE JR ANTHONY

US73 patents

⚠️ This page may combine multiple inventors who share the name “CORREALE JR ANTHONY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CORREALE JR ANTHONY

IBM

Systems and arrangements to interconnect components of a semiconductor device

On-chip power distribution for improved decoupling

Dynamic data bus allocation

Circuit for preserving data in a flip-flop and a method of use

System and method for creating a standard cell library for reduced leakage and improved performance

Memory by-pass for write through read operations

Systems and media to improve manufacturability of semiconductor devices

Methods, systems, and media to improve manufacturability of semiconductor devices

Dual-damascene metallization interconnection

Single supply level converter

Multiple voltage integrated circuit and design method therefor

Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator

Enhanced operational frequency for a precise and programmable duty cycle generator

Two-supply protection circuit

Memory defect steering circuit

Speed verification of an embedded processor in a programmable logic device

Process insensitive off-chip driver

Reduced power VLSI chip and driver circuit

Precise and programmable duty cycle generator

Performance built-in self test system for a device and a method of use

Adaptive execution cycle control method for enhanced instruction throughput

System and method for creating a standard cell library for use in circuit designs

Adaptive execution frequency control method for enhanced instruction throughput

Single supply level converter

Apparatus for measuring the duty cycle of a high speed clocking signal

Influence-based circuit design

Multiple voltage integrated circuit and design method therefor

Method and program product of level converter optimization

Top level hierarchy wiring via 1×N compiler

Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits

Scannable limited switch dynamic logic (LSDL) circuit

Voltage island circuit placement

Level translator circuit for power supply disablement

Dual damascene multi-level metallization

Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic

Method and circuit for optimizing power consumption and performance of driver circuits

Multiple duty cycle tap points for a precise and programmable duty cycle generator

Dual rail power supply sequence tolerant off-chip driver

By-pass boundary scan design

QUALCOMM INC

Standard cell architecture for diffusion based on fin count

Standard cell architecture for diffusion based on fin count

Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods

Mitigating length-of-diffusion effect for logic cells and placement thereof

Power distribution networks (PDNs) using hybrid grid and pillar arrangements

XILINX INC

Testing a programmable logic device with embedded fixed logic using a scan chain

CORREALE JR ANTHONY

Integrated design for manufacturing for 1×N VLSI design

BOWERS BENJAMIN J

Compiler for closed-loop 1×N VLSI design

BAKER MATTHEW W

Uniquification and parent-child constructs for 1xN VLSI design

STEINMETZ PAUL M

Hierarchy reassembler for 1×N VLSI design

MENTOR GRAPHICS CORP

Compiler for closed-loop 1×N VLSI design