Double side polished wafers having external gettering sites, and method of producing same

Abstract

A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.

What is claimed is:  
     
       1. A method of producing a double-side polished wafer containing extrinsic gettering sites on one side, comprising: 
       providing a semiconductor wafer, said wafer having a front surface and a back surface, wherein the back surface has been polished;  
       forming a polysilicon layer on the front surface and the back surface, said polysilicon layers containing oxygen;  
       forming a thermal oxide layer on each of the polysilicon layers, wherein the oxide layers consume the polysilicon layers;  
       stripping the thermal oxide layers off of the wafer; and  
       polishing the front side of the wafer.  
     
     
       2. The method of  claim 1 , wherein the back surface contains oxygen induced stacking faults to serve as extrinsic gettering sites. 
     
     
       3. The method of  claim 2  wherein the back surface contains at least 5*10 4  oxygen induced stacking faults per square centimeter. 
     
     
       4. The method of  claim 1 , wherein the polysilicon layers are between 50 Å and 500 Å in thickness. 
     
     
       5. The method of  claim 4 , wherein the polysilicon layers are deposited by chemical vapor deposition. 
     
     
       6. The method of  claim 5  wherein the polysilicon layers are deposited by low pressure chemical vapor deposition. 
     
     
       7. The method of  claim 1 , wherein the thermal, oxide layers are between 100 Å and 1000 Å in thickness. 
     
     
       8. The method of  claim 1  wherein the thermal oxide layers are formed at a temperature of between 850° C. and 1000° C. 
     
     
       9. The method of  claim 1 , wherein each of the back and front surfaces have a surface roughness of below 10 Å after polishing the front side of the wafer. 
     
     
       10. A method of producing a double-side polished wafer containing extrinsic gettering sites on one side, comprising: 
       providing a semiconductor wafer, said wafer having a front surface and a back surface, wherein the back surface has been polished;  
       forming a polysilicon layer on the front surface and the back surface, said polysilicon layers containing oxygen;  
       forming a thermal oxide layer on each of the polysilicon layers, wherein the oxide layers consume the polysilicon layers;  
       polishing the front side of the wafer; and  
       stripping the thermal oxide layer off of the back surface of the wafer.  
     
     
       11. The method of  claim 10 , wherein the back surface contains oxygen induced stacking faults to serve as extrinsic gettering sites. 
     
     
       12. The method of  claim 11 , wherein the back surface contains at least 5*10 4  oxygen induced stacking faults per square centimeter. 
     
     
       13. The method of  claim 10 , wherein the polysilicon layers are between 50 Å and 500 Å in thickness. 
     
     
       14. The method of  claim 13 , wherein the polysilicon layers are deposited by chemical vapor deposition. 
     
     
       15. The method of  claim 14 , wherein the chemical vapor deposition process is a low pressure chemical vapor deposition. 
     
     
       16. The method of  claim 10 , wherein the thermal oxide layers are between 100 Å and 1000 Å in thickness. 
     
     
       17. The method of  claim 10 , wherein the thermal oxide layers are formed at a temperature of between 850° C. and 1000° C. 
     
     
       18. The method of  claim 10 , wherein each of the back and front surfaces have a surface roughness of below 10 Å after polishing the front side of the wafer.