Methods of forming capacitors having a polymer on a portion thereof that inhibits the formation of hemispherical grain (HSG) nodules on that portion and capacitors formed thereby

Abstract

A capacitor includes an electrode that has an inner surface, an outer surface, and an end surface. At least one of the inner surface and the outer surface has hemispherical grain (HSG) nodules thereon, but the end surface is substantially devoid of HSG nodules. By maintaining the end surface of the electrode substantially devoid of HSG nodules, the mechanical strength and integrity of the end surface may not be degraded. Therefore, the frequency in which portions of the end surface break away during, for example, a cleaning process, and create electrical bridges with adjacent electrodes may be reduced.

We claim:  
     
       1. A method of forming a capacitor, comprising the steps of: 
       forming a polymer layer on an end surface of an electrode; and  
       forming hemispherical grain (HSG) nodules on at least one of an inner surface and an outer surface of the electrode while maintaining the end surface of the electrode, having the polymer layer formed thereon, as substantially devoid of HSG nodules.  
     
     
       2. A method as recited in  claim 1 , wherein the step of forming the polymer layer on the end surface of the electrode comprises: 
       forming the polymer layer on the end surface of the electrode and on corners of the electrode, which are defined by the intersection of the end surface with the inner surface and the outer surface, respectively; and  
       wherein the step of forming HSG nodules on at least one of the inner surface and the outer surface comprises the step of:  
       forming HSG nodules on at least one of the inner surface and the outer surface while maintaining the end surface and the corners of the electrode, having the polymer layer formed thereon, as substantially devoid of HSG nodules.  
     
     
       3. A method as recited in  claim 2 , wherein the step of forming a polymer layer on the end surface of the electrode and on the corners of the electrode comprises the step of: 
       performing a plasma treatment using a C x H y F z -series gas on the end surface of the electrode and on the corners of the electrode.  
     
     
       4. A method as recited in  claim 1 , further comprising the steps of: 
       forming a dielectric film on the electrode; and  
       forming a second electrode on the dielectric film opposite the electrode.  
     
     
       5. A method of forming a capacitor, comprising the steps of: 
       forming an inter-electrode insulating pattern;  
       etching a trench in the inter-electrode insulating pattern;  
       forming a silicon layer on the inter-electrode insulating pattern and in the trench, the silicon layer comprising a first electrode of the capacitor and having an inner surface and an outer surface;  
       forming an insulating layer on the silicon layer;  
       planarizing the insulating layer, the silicon layer, and the inter-electrode insulating pattern so as to form and expose an end surface of the silicon layer;  
       forming a polymer layer on the end surface of the silicon layer;  
       removing at least one of the insulating layer and the inter-electrode insulating pattern; and  
       forming hemispherical grain (HSG) nodules on at least one of the inner surface of the silicon layer and the outer surface of the silicon layer, while maintaining the end surface of the silicon layer, having the polymer layer formed thereon, as substantially devoid of HSG nodules.  
     
     
       6. A method as recited in  claim 5 , wherein the inter-electrode insulating pattern comprises a material selected from the group consisting of phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), undoped silicate glass (USG), plasma enhanced tetra ethyl ortho silicate (PE-TEOS), and silicon oxide (SiO 2 ). 
     
     
       7. A method as recited in  claim 5 , wherein the insulating layer comprises a material selected from the group consisting of undoped silicate glass (USG), phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PE-TEOS), hydro silses Quioxane (HSQ), spin-on-glass (SOG), and photoresist. 
     
     
       8. A method as recited in  claim 5 , wherein the step of forming a silicon layer on the inter-electrode insulating pattern comprises the steps of: 
       depositing the silicon layer amorphously on the inter-electrode insulating pattern by chemical vapor deposition (CVD); and  
       doping the silicon layer with impurities during CVD.  
     
     
       9. A method as recited in  claim 8 , wherein the impurities are selected from the group consisting of phosphorous (P) and arsenic (As) ions. 
     
     
       10. A method as recited in  claim 8 , wherein an impurity concentration is substantially uniform throughout the silicon layer. 
     
     
       11. A method as recited in  claim 8 , wherein an impurity concentration is non-uniform throughout the silicon layer. 
     
     
       12. A method as recited in  claim 5 , wherein the step of planarizing the insulating layer, the silicon layer, and the inter-electrode insulating pattern comprises the step of: 
       chemical mechanical polishing the insulating layer, the silicon layer, and the inter-electrode insulating pattern so as to form and expose the end surface of the silicon layer.  
     
     
       13. A method as recited in  claim 5 , wherein the step of planarizing the insulating layer, the silicon layer, and the inter-electrode insulating pattern comprises the step of: 
       performing a dry etch-back process using a C x F y -series gas on the insulating layer, the silicon layer, and the inter-electrode insulating pattern so as to form and expose the end surface of the silicon layer.  
     
     
       14. A method as recited in  claim 13 , wherein the C x F y -series gas is selected from the group consisting of CF 4 , C 2 F 6 , and C 4 F 8 . 
     
     
       15. A method as recited in  claim 5 , wherein the step of forming a polymer layer on the end surface of the silicon layer comprises the step of: 
       forming the polymer layer on the end surface of the silicon layer and corners of the silicon layer, which are defined by the intersection of the end surface with the inner surface and the outer surface, respectively.  
     
     
       16. A method as recited in  claim 5 , wherein the step of forming a polymer layer on the end surface of the silicon layer comprises the step of: 
       treating the insulating layer, the end surface of the silicon layer, and the inter-electrode insulating pattern with a plasma so as to etch the insulating layer and the inter-electrode insulating pattern.  
     
     
       17. A method as recited in  claim 16 , wherein the plasma comprises a C x H y F y -series gas. 
     
     
       18. A method as recited in  claim 17 , wherein the plasma is a gas selected from the group consisting of CHF 3  and CH 2 F 2 . 
     
     
       19. A method as recited in  claim 18 , wherein the insulating layer and the inter-electrode insulating pattern comprise different materials having a high etching selectivity therebetween with respect to a predetermined etchant. 
     
     
       20. A method as recited in  claim 5 , wherein the step of removing at least one of the insulating layer and the inter-electrode insulating pattern comprises the step of: 
       removing the insulating layer; and  
       wherein the step of forming HSG nodules on at least one of the inner surface of the silicon layer and the outer surface of the silicon layer comprises the step of:  
       forming HSG nodules on the inner surface of the silicon layer.  
     
     
       21. A method as recited in  claim 5 , wherein the step of removing at least one of the insulating layer and the inter-electrode insulating pattern comprises the step of: 
       removing the inter-electrode insulating pattern; and  
       wherein the step of forming HSG nodules on at least one of the inner surface of the silicon layer and the outer surface of the silicon layer comprises the step of:  
       forming HSG nodules on the outer surface of the silicon layer.  
     
     
       22. A method as recited in  claim 21 , wherein the insulating layer and the inter-electrode insulating pattern comprise different materials having a high etching selectivity therebetween with respect to a predetermined etchant. 
     
     
       23. A method as recited in  claim 5 , further comprising the following steps after the step of forming HSG nodules on at least one of the inner surface of the silicon layer and the outer surface of the silicon layer: 
       forming a dielectric film on the silicon layer; and  
       forming a second electrode on the dielectric film opposite the first electrode.  
     
     
       24. A method as recited in  claim 23 , further comprising the following step before the step of forming the dielectric film on the silicon layer: 
       cleaning the silicon layer.  
     
     
       25. A method as recited in  claim 5 , further comprising the following steps before the step of forming an inter-electrode insulating pattern: 
       providing an interlayer insulating layer;  
       forming an etch stop layer on the interlayer insulating layer;  
       forming a trench in the interlayer insulating layer and the etch stop layer; and  
       forming a contact plug in the trench.  
     
     
       26. A method as recited in  claim 25 , wherein the step of forming an inter-electrode insulating pattern comprises the step of: 
       forming an inter-electrode insulating pattern on the etch stop layer and the contact plug;  
       wherein the step of etching a trench in the inter-electrode insulating pattern comprises the step of:  
       etching the trench in the inter-electrode insulating pattern so as to expose the contact plug;  
       wherein the step of forming a silicon layer on the inter-electrode insulating pattern and in the trench comprises the step of:  
       forming the silicon layer on the inter-electrode insulating layer and in the trench so as to contact the contact plug.