Semiconductor device with SRAM section including a plurality of memory cells

Abstract

A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

What is claimed is:  
     
       1. A semiconductor device, comprising: 
       an SRAM section which includes a plurality of memory cells, wherein each of the memory cells comprises:  
       a first well of a primary conductivity type,  
       a second well of a secondary conductivity type,  
       a first load transistor and a second load transistor,  
       a first driver transistor and a second driver transistor,  
       a first access transistor and a second access transistor,  
       wherein the first and second load transistors are located on the first well,  
       wherein the first and second driver transistors and the first and second access transistors are located on the second well; and  
       a third well of the primary conductivity type, wherein a bottom section of the third well is located at a position deeper than bottom sections of the first and second wells, wherein the third well is connected to the first well in each of the memory cells, wherein:  
       each of the memory cells has first and second gate-gate electrode layeres, first and second drain-drain connecting layers, and first and second drain-gate connecting layers;  
       the first gate-gate electrode layer includes gate electrodes of the first load transistor and the first driver transistor;  
       the second gate-gate electrode layer includes gate electrodes of the second load transistor and the second driver transistor;  
       the first drain-drain connecting layer connects a drain of the first load transistor with a drain of the first driver transistor;  
       the second drain-drain connecting layer connects a drain of the second load transistor with a drain of the second driver transistor;  
       the first and second gate-gate electrode layers are located between the first and second drain-drain connecting layers;  
       the first drain-gate connecting layer connects the first drain-drain connecting layer with the second gate-gate electrode layer;  
       the second drain-gate connecting layer connects the second drain-drain connecting layer with the first gate-gate electrode layer; and  
       each of the drain-gate connecting layers, the drain-drain connecting layers, and the gate-gate electrode layers is located in different layers.  
     
     
       2. The semiconductor device as defined in  claim 1 , further comprising a semiconductor circuit section, wherein: 
       the semiconductor circuit section comprises a fourth well of the primary conductivity type; and  
       the fourth well is connected to the third well.  
     
     
       3. The semiconductor device as defined in  claim 1 , wherein: 
       the SRAM section includes a normal memory cell group and a redundant memory cell group; and  
       the normal memory cell group is able to be replaced by the redundant memory cell group.  
     
     
       4. The semiconductor device as defined in  claim 3 , wherein: 
       each of the memory cells has a power supply line for a cell;  
       the power supply line for a cell supplies a potential to the first and second load transistors in each of the memory cells;  
       the power supply line for a cell is electrically isolated from the third well;  
       each of the normal and redundant memory cell groups has a power supply line for a memory cell group;  
       the power supply line for a memory cell group supplies a potential to the first and second load transistors in each of the memory cells;  
       the power supply line for a cell is electrically isolated from the third well;  
       each of the normal and redundant memory cell groups has a power supply line for a memory cell group;  
       the power supply line for a memory cell group supplies a potential to the power supply lines for a cell in each of the normal and redundant memory cell groups;  
       the power supply line for a memory cell group includes a power supply disconnecting circuit; and  
       the power supply line for a cell is able to be disconnected from a power supply by the power supply disconnecting circuit.  
     
     
       5. The semiconductor device as defined in  claim 4 , wherein: 
       the power supply line for a memory cell group supplies a potential to a bit-line precharge circuit for each of the memory cells; and  
       the bit-line precharge circuit is able to be disconnected from a power supply by the power supply disconnecting circuit.  
     
     
       6. The semiconductor device as defined in  claim 4 , wherein: 
       the plurality of memory cells makes up a memory cell array; and  
       each of the normal and redundant memory cell groups includes a plurality of columns of the memory cells in the memory cell array.  
     
     
       7. The semiconductor device as defined in  claim 1 , wherein: 
       the primary conductivity type is an n-type;  
       the secondary conductivity type is a p-type;  
       a V DD  power supply is connected to the first and third wells; and  
       a V SS  power supply is connected to the second well.  
     
     
       8. The semiconductor device as defined in  claim 1 , 
       wherein a well contact region is provided for every two memory cells in the second well.  
     
     
       9. A semiconductor device, comprising: 
       an SRAM section which includes a plurality of memory cells, wherein each of the memory cells comprises: a first well of a primary conductivity type; a second well of a secondary conductivity type; a first load transistor and a second load transistor, wherein the first and second load transistors are a first driver transistor and a second driver transistor, wherein the first and second driver transistors are located on the second well; a first access transistor and a second access transistor, wherein the first and second access transistors are located on the second well; and a third well of the primary conductivity type, wherein a bottom section of the third well is located at a position deeper than bottom sections of the first and second wells, and wherein the third well is connected to the first well in each of the memory cells; and  
       a semiconductor circuit section comprising a fourth well of the primary conductivity type, wherein the fourth well is connected to the third well.  
     
     
       10. The semiconductor device as defined in  claim 9 , 
       wherein the SRAM section has no well contact region in the third well.  
     
     
       11. The semiconductor device as defined in  claim 9 , 
       wherein the SRAM section has a well contact region in the third well.  
     
     
       12. The semiconductor device as defined in  claim 9 , wherein: 
       the SRAM section includes a normal memory cell group and a redundant memory cell group; and  
       the normal memory cell group is able to be replaced by the redundant memory cell group.  
     
     
       13. The semiconductor device as defined in  claim 12 , wherein: 
       each of the memory cells has a power supply line for a cell;  
       the power supply line for a cell supplies a potential to the first and second load transistors in each of the memory cells;  
       the power supply line for a cell is electrically isolated from the third well;  
       each of the normal and redundant memory cell groups has a power supply line for a memory cell group;  
       the power supply line for a memory cell group supplies a potential to the power supply lines for a cell in each of the normal and redundant memory cell groups;  
       the power supply line for a memory cell group includes a power supply disconnecting circuit; and  
       the power supply line for a cell is able to be disconnected from a power supply by the power supply disconnecting circuit.  
     
     
       14. The semiconductor device as defined in  claim 13 , wherein: 
       the power supply line for a memory cell group supplies a potential to a bit-line precharge circuit for each of the memory cells; and  
       the bit-line precharge circuit is able to be disconnected from a power supply by the power supply disconnecting circuit.  
     
     
       15. The semiconductor device as defined in  claim 12 , wherein: 
       the plurality of memory cells makes up a memory cell array; and  
       each of the normal and redundant memory cell groups includes a plurality of columns of the memory cells in the memory cell array.  
     
     
       16. The semiconductor device as defined in  claim 9 , wherein: 
       each of the memory cells has first and second gate-gate electrode layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers;  
       the first gate-gate electrode layer includes gate electrodes of the first load transistor and the first driver transistor;  
       the second gate-gate electrode layer includes gate electrodes of the second load transistor and the second driver transistor;  
       the first drain-drain connecting layer connects a drain of the first load transistor with a drain of the first driver transistor;  
       the second drain-drain connecting layer connects a drain of the second load transistor with a drain of the second driver transistor;  
       the first and second gate-gate electrode layers are located between the first and second drain-drain connecting layers;  
       the first drain-gate connecting layer connects the first drain-drain connecting layer with the second gate-gate electrode layer;  
       the second drain-gate connecting layer connects the second drain-drain connecting layer with the first gate-gate electrode layer; and  
       each of the drain-gate connecting layers, the drain-drain connecting layers, and the gate-gate electrode layers is located in different layers.  
     
     
       17. The semiconductor device as defined in  claim 9 , wherein: 
       the primary conductivity type is an n-type;  
       the secondary conductivity type is a p-type;  
       a  VDD  power supply is connected to the first and third wells; and  
       a  VSS  power supply is connected to the second well.  
     
     
       18. The semiconductor device as defined in  claim 9 , 
       wherein a well contact region is provided for every two memory cells in the second well.  
     
     
       19. A semiconductor device, comprising: 
       an SRAM section which includes a plurality of memory cells, wherein each of the memory cells comprises:  
       a first well of a primary conductivity type;  
       a second well of a secondary conductivity type;  
       a first load transistor and a second load transistor, wherein the first and second load transistors are located on the first well;  
       a first driver transistor and a second driver transistor, wherein the first and second driver transistors are located on the second well;  
       a first access transistor and a second access transistor, wherein the first and second access transistors are located onto the second well; and  
       a third well of the primary conductivity type, wherein a bottom section of the third well is located at a position deeper than bottom sections of the first and second well, wherein the third well is connected to the first well in each of the memory cells,  
       wherein the SRAM section includes a normal memory cell group and a redundant memory cell group, wherein the normal memory cell group is able to be replaced by the redundant memory cell group.  
     
     
       20. The semiconductor device as defined in  claim 19 , wherein the SRAM section has no well contact region in the third well. 
     
     
       21. The semiconductor device as defined in  claim 19 , wherein the SRAM section has a well contact region in the third well. 
     
     
       22. The semiconductor device as defined in  claim 19 , wherein: 
       each of the memory cells has a power supply line for a cell;  
       the power supply line for a cell supplies a potential to the first and second load transistors in each of the memory cells;  
       the power supply line for a cell is electrically isolated from the third well;  
       each of the normal and redundant memory cell groups has a power supply line for a memory cell group;  
       the power supply line for a memory cell group supplies a potential to the power supply lines for a cell in each of the normal and redundant memory cell groups;  
       the power supply line for a memory cell group includes a power supply disconnecting circuit; and  
       the power supply line for a cell is able to be disconnected from a power supply by the power supply disconnecting circuit.  
     
     
       23. The semiconductor device as defined in  claim 22 , wherein: 
       the power supply line for a memory cell group supplies a potential to a bit-line precharge circuit for each of the memory cells; and  
       the bit-line precharge circuit is able to be disconnected for a power supply by the power supply disconnecting circuit.  
     
     
       24. The semiconductor device as defined in  claim 19 , wherein: 
       the plurality of memory cells makes up a memory cell array; and  
       each of the normal and redundant memory cell groups includes a plurality of columns of the memory cells in the memory cell array.  
     
     
       25. The semiconductor device as defined in  claim 19 , wherein: 
       each of the memory cells has first and second gate-gate electrode layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers;  
       the first gate-gate electrode layer includes gate electrodes of the first load transistor and the first driver transistor;  
       the second gate-gate electrode layer includes gate electrodes of the second load transistor and the second driver transistor;  
       the first drain-drain connecting layer connects a drain of the second load transistor with a drain of the second driver transistor;  
       the second drain-drain connecting layer connects a drain of the second load transistor with a drain of the second driver transistor;  
       the first and second gate-gate electrode layers are located between the first and second drain-drain connecting layers;  
       the first drain-gate connecting layer connects the first drain-drain connecting layer with the second gate-gate electrode layer;  
       the second drain-gate connecting layer connects the second drain-drain connecting layer with the first gate-gate electrode layer; and  
       each of the drain-gate connecting layers, the drain-drain connecting layers, and the gate-gate electrode layers is located in different layers.  
     
     
       26. The semiconductor device as defined in  claim 19 , wherein: 
       the primary conductivity type is an n-type;  
       the secondary conductivity type is a p-type;  
       a  VDD  power supply is connected to the first and third wells; and  
       a  VSS  power supply is connected to the second well.  
     
     
       27. The semiconductor device as defined in  claim 19 , wherein a well contact region is provided for every two memory cells in the second well.