Counter with non-uniform digit base

Abstract

A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

What is claimed is:  
     
       1. A counter comprising: 
       a nonvolatile storage organized in digits having non-uniform bases and a  
       respective number of bits according to its base minus one; and  
       circuitry to increment a count value represented by the digits in response to an increment command.  
     
     
       2. The counter of  claim 1  wherein the nonvolatile storage includes a plurality of blocks of storage cells, each of the digits being stored in a respective one of the blocks. 
     
     
       3. The counter of  claim 2  wherein one of the digits spans two or more of the blocks. 
     
     
       4. The counter of  claim 2  wherein the nonvolatile storage is a flash erasable programmable read only memory in which a selected block of the plurality of blocks is erased in response to an erase command that identifies the selected block. 
     
     
       5. The counter of  claim 1  wherein the circuitry includes circuitry to increment one of the digits and to erase each of the digits less significant than the one of the digits. 
     
     
       6. The counter of  claim 5  wherein the circuitry to erase each of the digits less significant than the one of the digits comprises circuitry to concurrently erase each of the digits less significant than the one of the digits. 
     
     
       7. A counter comprising: 
       a nonvolatile storage organized in digits having non-uniform bases, and  
       circuitry to increment a count value represented by the digits in response to an increment command, the circuitry to increment a count value including:  
       circuitry to increment one digit of the digits by programming only one bit of the one digit and evaluate bits of the one digit to identify a least significant bit of the one digit that is in an erased state, the least significant bit being the only one bit programmed to increment the one digit.  
     
     
       8. A counter comprising: 
       nonvolatile storage organized in digits having non-uniform bases;  
       circuitry to increment a count value represented by the digits in response to an increment command; and  
       configuration circuitry to receive a counter setup command, to allocate regions of the nonvolatile storage to the digits according to the counter setup command and store setup information specified in the setup command in a region of the nonvolatile storage.  
     
     
       9. The counter of  claim 8  wherein the region of the nonvolatile storage where the setup information is stored is a one-time programmable region that cannot be erased. 
     
     
       10. The counter of  claim 8  further comprising initialization circuitry to read the setup information in the region of the nonvolatile storage to identify the digits of the counter. 
     
     
       11. A counter comprising: 
       nonvolatile storage organized in digits having non-uniform bases; and  
       circuitry to increment a count value by one causing the count value to be reduced by one in response to an increment command.  
     
     
       12. A counter comprising: 
       nonvolatile storage organized in digits having non-uniform bases;  
       circuitry to increment a count value represented by the digits in response to an increment command; and  
       circuitry to prevent erasure of the digits in response to detecting that a maximum count of the counter has been reached.  
     
     
       13. A counter comprising: 
       nonvolatile storage organized in digits having non-uniform bases;  
       circuitry to increment a count value represented by the digits in response to an increment command,  
       program circuitry to write data to the nonvolatile storage in response to  
       program commands received from an external source; and  
       circuitry to detect whether an address specified by one of the program commands falls within a range of the nonvolatile storage allocated to the digits and to disallow the program circuitry from writing data at the address.  
     
     
       14. The counter of  claim 13  further comprising circuitry to output the count value represented by the digits in response to the increment command. 
     
     
       15. The counter of  claim 13  further comprising circuitry to output the count value represented by the digits in response to a read counter command. 
     
     
       16. The counter of  claim 13  further comprising circuitry to generate a binary representation of the count value for output to a host processor. 
     
     
       17. The counter of  claim 16  wherein the circuitry to generate a binary representation of the count value is configured to generate a distinct binary representation of the value of each of the digits. 
     
     
       18. A counter comprising: 
       nonvolatile storage organized in digits having non-uniform bases;  
       circuitry to increment a count value represented by the digits in response to an increment command; and  
       program circuitry to write data to the nonvolatile storage in response to program commands received from an external source.  
     
     
       19. The counter of  claim 18  further comprising circuitry to detect whether an address specified by one of the program commands falls within a range of the nonvolatile storage allocated to the digits and to disallow the program circuitry from writing data at the address. 
     
     
       20. The counter of  claim 18  wherein the nonvolatile storage includes a plurality of blocks of storage cells, each of the digits being stored in a respective one of the blocks. 
     
     
       21. The counter of  claim 20  wherein one of the digits spans two or more of the blocks. 
     
     
       22. The counter of  claim 20  wherein the nonvolatile storage is a flash erasable programmable read only memory in which a selected block of the plurality of blocks is erased in response to an erase command that identifies the selected block. 
     
     
       23. The counter of  claim 18  wherein the circuitry includes circuitry to increment one of the digits and to erase each of the digits less significant than the one of the digits. 
     
     
       24. The counter of  claim 23  wherein the circuitry to erase each of the digits less significant than the one of the digits comprises circuitry to concurrently erase each of the digits less significant than the one of the digits.