Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks

Abstract

An apparatus including a MOSFET circuit having dual threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.

What is claimed is:  
     
       1. An apparatus comprising: 
       a MOSFET circuit having dual threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.  
     
     
       2. The apparatus of  claim 1 , wherein the threshold voltage of the low threshold voltage NMOS transistor is set with an implantation comprising an implanted material comprising one of the group consisting of arsenic, phosphorous and antimony. 
     
     
       3. The apparatus of  claim 1 , wherein the threshold voltage of the high threshold voltage PMOS transistor is set with an implantation comprising an implanted material comprising one of the group consisting of boron and boron difluoride. 
     
     
       4. The apparatus of  claim 1 , wherein the threshold voltage of the high threshold voltage NMOS transistor is enhanced, and the threshold voltage of the low threshold voltage PMOS transistor is compensated, with an implantation comprising an implanted material comprising one of the group consisting of arsenic, phosphorous and antimony.