Semiconductor device with silicon-carbon-oxygen dielectric having improved metal barrier adhesion and method of forming the device

Abstract

A method ( 100 ) of fabricating an electronic device ( 200 ) formed on a semiconductor wafer. The method forms a dielectric layer ( 226 ) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes ( 118 ) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer ( 120 ) adjacent at least a portion of the dielectric layer.

What is claimed is:  
     
       1. A method of fabricating an electronic device formed on a semiconductor wafer, comprising the steps of: 
       forming a dielectric layer in a fixed position relative to the wafer, the dielectric layer comprising an atomic concentration of each of silicon, carbon, and oxygen;  
       after the forming step, exposing the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased; and  
       after the exposing step, forming a barrier layer adjacent at least a portion of the dielectric layer.  
     
     
       2. The method of  claim 1  wherein the exposing step comprises exposing the electronic device to a plasma comprising helium and hydrogen. 
     
     
       3. The method of  claim 1  wherein the exposing step comprises exposing the electronic device to a plasma comprising helium and H 2 . 
     
     
       4. The method of  claim 3  wherein the plasma comprises approximately 95% of helium and approximately 5% of H 2 . 
     
     
       5. The method of  claim 1  wherein the exposing step comprises: 
       applying a power of at least 100 Watts to a pedestal supporting the wafer; and  
       at a same time as the applying step, exposing the electronic device to a plasma comprising helium and hydrogen.  
     
     
       6. The method of  claim 1  wherein the exposing step comprises: 
       applying a power in a range between 100 and 500 Watts to a pedestal supporting the wafer; and  
       at a same time as the applying step, exposing the electronic device to a plasma comprising helium and hydrogen.  
     
     
       7. The method of  claim 1  and further comprising: 
       forming a conductor in a fixed position relative to the wafer and prior to the step of forming a dielectric layer such that the step of forming a dielectric layer forms the dielectric layer such that the conductor is positioned between the wafer and the dielectric layer; and  
       forming a void in the dielectric layer prior to the exposing step, wherein the void extends through the dielectric layer and exposes a portion of the conductor.  
     
     
       8. The method of  claim 7  and further comprising, after the step of forming a void and prior to the step of exposing the electronic device to a plasma, exposing the electronic device to argon. 
     
     
       9. The method of  claim 7  wherein the step of forming a barrier layer comprises forming a metal barrier layer. 
     
     
       10. The method of  claim 9  wherein the metal barrier layer comprises tantalum. 
     
     
       11. The method of  claim 9  and further comprising, after the step of forming a barrier layer, a step of forming a metal layer adjacent the barrier layer. 
     
     
       12. The method of  claim 11  wherein the step of forming a metal layer comprises forming a copper layer. 
     
     
       13. The method of  claim 12  and further comprising, after the step of forming a barrier layer and before the step of forming a metal layer, forming a metal seed layer. 
     
     
       14. The method of  claim 13 : 
       wherein the metal seed layer comprises forming a copper seed layer; and  
       wherein the step of forming a copper layer comprises plating the copper layer.  
     
     
       15. The method of  claim 11  and further comprising a step of planarizing the metal layer, a portion of the metal barrier layer, and a portion of the dielectric layer. 
     
     
       16. The method of  claim 1  wherein the dielectric layer comprises a first dielectric layer, and further comprising, prior to the exposing step, a step of forming a second dielectric layer in a fixed position relative to the first dielectric layer such that the first dielectric layer is positioned between the second dielectric layer and the wafer, the second dielectric comprising an atomic concentration of each of silicon, carbon, and oxygen. 
     
     
       17. The method of  claim 16  wherein, in response to the exposing step, the atomic concentration of carbon in a portion of the second dielectric layer is increased and the atomic concentration of oxygen in a portion of the second dielectric is decreased. 
     
     
       18. The method of  claim 17  wherein the exposing step comprises exposing the electronic device to a plasma comprising helium and hydrogen. 
     
     
       19. The method of  claim 17  wherein the exposing step comprises exposing the electronic device to a plasma comprising helium and H 2 . 
     
     
       20. The method of  claim 19  wherein the plasma comprises approximately  95 % of helium and approximately 5% of H 2 . 
     
     
       21. The method of  claim 17  wherein the exposing step comprises: 
       applying a power of at least 100 Watts to a pedestal supporting the wafer; and  
       at a same time as the applying step, exposing the electronic device to a plasma comprising helium and hydrogen.  
     
     
       22. The method of  claim 17  wherein the exposing step comprises: 
       applying a power in a range between 100 and 500 Watts to a pedestal supporting the wafer; and  
       at a same time as the applying step, exposing the electronic device to a plasma comprising helium and hydrogen.  
     
     
       23. The method of  claim 17  and further comprising: 
       forming a conductor in a fixed position relative to the wafer and prior to the step of forming a first dielectric layer such that the step of forming a first dielectric layer forms the first dielectric layer such that the conductor is positioned between the wafer and the first dielectric layer; and  
       forming a void in the first and second dielectric layers prior to the exposing step, wherein the void extends through the first and second dielectric layers and exposes a portion of the conductor.  
     
     
       24. The method of  claim 23  and further comprising, after the step of forming a void and prior to the step of exposing the electronic device to a plasma, exposing the electronic device to argon. 
     
     
       25. The method of  claim 24  wherein the step of forming a barrier layer comprises forming a metal barrier layer. 
     
     
       26. The method of  claim 25  wherein the metal barrier layer comprises tantalum. 
     
     
       27. The method of  claim 25  and further comprising, after the step of forming a barrier layer, a step of forming a metal layer adjacent the barrier layer. 
     
     
       28. The method of  claim 27  wherein the step of forming a metal layer comprises forming a copper layer. 
     
     
       29. The method of  claim 26  and further comprising, after the step of forming a barrier layer and before the step of forming a metal layer, forming a metal seed layer. 
     
     
       30. The method of  claim 29 : 
       wherein the metal seed layer comprises forming a copper seed layer; and  
       wherein the step of forming a copper layer comprises plating the copper layer.  
     
     
       31. The method of  claim 1  wherein the step of forming a barrier layer comprises forming a metal barrier layer. 
     
     
       32. The method of  claim 31  wherein the metal barrier layer comprises tantalum. 
     
     
       33. The method of  claim 31  and further comprising, after the step of forming a barrier layer, a step of forming a metal layer adjacent the barrier layer. 
     
     
       34. The method of  claim 33  wherein the step of forming a metal layer comprises forming a copper layer. 
     
     
       35. The method of  claim 34  and further comprising, after the step of forming a barrier layer and before the step of forming a metal layer, forming a metal seed layer. 
     
     
       36. The method of  claim 35 : 
       wherein the metal seed layer comprises forming a copper seed layer; and of forming a copper layer comprises plating the copper layer.  
     
     
       37. The method of  claim 33  and further comprising a step of planarizing the metal layer, a portion of the metal barrier layer, and a portion of the dielectric layer. 
     
     
       38. A method of fabricating an electronic device formed on a semiconductor wafer, comprising the steps of: 
       forming a dielectric layer in a fixed position relative to the wafer, the dielectric layer comprising silicon, carbon, and oxygen;  
       after the forming step, exposing the electronic device to a plasma comprising helium and hydrogen; and  
       after the exposing step, forming a barrier layer adjacent at least a portion of the dielectric layer.  
     
     
       39. The method of  claim 38  wherein the exposing step comprises: 
       applying a power of at least 100 Watts to a pedestal supporting the wafer; and  
       at a same time as the applying step, exposing the electronic device to a plasma comprising helium and hydrogen.  
     
     
       40. The method of  claim 39  and further comprising: 
       forming a conductor in a fixed position relative to the water and prior to the step of forming a dielectric layer such that the step of forming a dielectric layer forms the dielectric layer such that the conductor is positioned between the wafer and the dielectric layer; and  
       forming a void in the dielectric layer prior to the exposing step, wherein the void extends through the dielectric layer and exposes a portion of the conductor.  
     
     
       41. The method of  claim 40  and further comprising, after the step of forming a void and prior to the step of exposing the electronic device to a plasma, exposing the electronic device to argon. 
     
     
       42. The method of  claim 41  wherein the step of forming a barrier layer comprises forming a metal barrier layer. 
     
     
       43. The method of  claim 42  and further comprising, after the step of forming a barrier layer, a step of forming a metal layer adjacent the barrier layer. 
     
     
       44. The method of  claim 43  wherein the step of forming a metal layer comprises forming a copper layer. 
     
     
       45. The method of  claim 44  and further comprising, after the step of forming a barrier layer and before the step of forming a metal layer, forming a metal seed layer. 
     
     
       46. The method of  claim 45 : 
       wherein the metal seed layer comprises forming a copper seed layer; and  
       wherein the step of forming a copper layer comprises plating the copper layer.  
     
     
       47. The method of  claim 43  and further comprising a step of planarizing the metal layer, a portion of the metal barrier layer, and a portion of the dielectric layer.