NROM cell with N-less channel

Abstract

A method of fabricating nitride read-only memory (NROM) cells and arrays. The memory device is formed on a substrate. Each memory cell comprises a pair of bit lines extending in a first direction across the substrate, a pair of bit line dielectrics overlaying and covering the pair of bit lines, a charge-trapping layer formed over the channel region between the pair of bit lines, and a conductive connecting block formed on the charge-trapping layer. The charge-trapping layer comprising two oxide-nitride-oxide (ONO) structures separated by a gate oxide layer, where each ONO structures comprises a layer of nitride sandwiched between a bottom oxide layer and a top oxide layer. A plurality of straight, parallel-edged word lines extend across the substrate in a second direction and cross over the bit lines and channel regions. Each word line comprises a conductive material and is separated from the substrate by the conductive connecting blocks and bit lines dielectrics.

What is claimed is:  
     
       1. A method of forming a semiconductor structure, comprising: 
       forming a charge-trapping structure on a substrate; wherein said charge-trapping structure comprises:  
       (i) a first ONO structure on a first portion of said substrate:  
       (ii) a second ONO structure on a second portion of said substrate, wherein said first portion does not completely overlap said second portion; and  
       (iii) a gate oxide between said first and second ONO structures; and  
       said ONO structures comprise a nitride layer between a first oxide layer and a second oxide layers and are formed by:  
       forming an oxide-conductive layer on said substrate, said oxide-conductive layer comprising a first conductive layer on a thick oxide layer;  
       laying down a bit line mask of photoresist, said bit line mask formed generally in columns at least within a memory portion of said substrate;  
       removing at least a portion of said oxide-conductive layer wherever said photoresist is not present to form oxide-conductive-layer columns comprising said gate;  
       implanting bit lines wherever said photoresist is not present and generally in columns;  
       removing said photoresist;  
       removing a portion of said remaining thick oxide layer from said oxide-conductive-layer columns to form a recess and said gate oxide;  
       growing a thin oxide layer over said memory portion of said substrate, the portion of said thin oxide layer in the lower region of said recess forming said first oxide layer and the portion of said thin oxide layer in the upper region of said recess forming said second oxide layer;  
       depositing a nitride layer over said thin oxide layer to a thickness sufficient to fill said recess; and  
       removing said nitride layer except in the region of said recess to form said ONO structures.  
     
     
       2. The method of  claim 1 , further comprising: 
       forming bit line dielectrics on said bit lines; and  
       removing said thin oxide layer from the top surface of said oxide-conductive-layer columns.  
     
     
       3. The method of  claim 2 , further comprising depositing a second conductive layer on said substrate. 
     
     
       4. The method of  claim 3 , further comprising concurrently etching said first and second conductive layers to form word lines perpendicular to and on said bit line dielectrics and said oxide-conductive-layer columns. 
     
     
       5. A method of forming a semiconductor device, comprising: 
       making a semiconductor structure by the method of  claim 1 ; and  
       forming a semiconductor device from said semiconductor structure.  
     
     
       6. A method of making an electronic device, comprising: 
       making a semiconductor device by the method of  claim 5 ; and forming an electronic device comprising said semiconductor device.  
     
     
       7. A method of forming a semiconductor device, comprising: 
       making a semiconductor structure by the method of  claim 1 ; and  
       forming a semiconductor device from said semiconductor structure.  
     
     
       8. A method of making an electronic device, comprising: 
       making a semiconductor device by the method of  claim 7 ; and forming an electronic device comprising said semiconductor device.  
     
     
       9. A method of forming a semiconductor structure, comprising: 
       forming a charge-trapping structure on a substrate; wherein said charge-trapping structure comprises:  
       (i) a first ONO structure on a first portion of said substrate;  
       (ii) a second ONO structure on a second portion of said substrate, wherein said first portion does not completely overlap said second portion; and  
       (iii) a gate oxide between said first and second ONO structures; and  
       said ONO structures comprise a nitride layer between a first oxide layer and a second oxide layer and are formed by:  
       forming an oxide-conductive layer on said substrate, said oxide-conductive layer comprising a first conductive layer on a thick oxide layer;  
       laying down a bit line mask of photoresist, said bit line mask formed generally in columns at least within a memory portion of said substrate;  
       removing at least a portion of said oxide-conductive layer wherever said photoresist is not present to form oxide-conductive layer columns comprising said gate on said gate oxide;  
       implanting bit lines wherever said photoresist is not present and generally in columns;  
       removing said photoresist; and  
       forming an ONO layer within said memory portion of said substrate, said ONO layer comprising said nitride layer between said first oxide layer and said second oxide layer;  
       removing said ONO layer except from the regions adjacent to said oxide-conductive-layer columns to form said ONO structures.  
     
     
       10. The method of  claim 9 , further comprising: 
       forming bit line dielectrics on said bit lines and said ONO structures; and  
       removing said thin oxide layer from the top surface of said oxide-conductive-layer columns.  
     
     
       11. The method of  claim 10 , further comprising depositing a second conductive layer on said substrate. 
     
     
       12. The method of  claim 11 , further comprising concurrently etching said first and second conductive layers to form word lines perpendicular to and on said bit line dielectrics and said oxide-conductive-layer columns. 
     
     
       13. A method of forming a semiconductor device, comprising: 
       making a semiconductor structure by the method of  claim 9 ; and  
       forming a semiconductor device from said semiconductor structure.  
     
     
       14. A method of making an electronic device, comprising: 
       making a semiconductor device by the method of  claim 9 ; and  
       forming an electronic device comprising said semiconductor device.  
     
     
       15. A method of forming a semiconductor structure, comprising; 
       forming a charge-trapping structure on a substrate; wherein said charge-trapping structure comprises:  
       (i) a first ONO structure on a first portion of said substrate;  
       (ii) a second ONO structure on a second portion of said substrate, wherein said first portion does not completely overlap said second portion; and  
       (iii) a gate oxide between said first and second ONO structures; and  
       said ONO structures comprise a nitride layer between a first oxide layer and a second oxide layer and are formed by:  
       forming an oxide-conductive layer on said substrate, said oxide-conductive layer comprising a first conductive layer on a thick oxide layer;  
       within a memory portion of said substrate, removing at least a portion of said oxide-conductive layer to form oxide-conductive-layer columns comprising said gate;  
       implanting bit lines between said oxide-conductive-layer columns;  
       removing a portion of said remaining thick oxide layer from said oxide-conductive-layer columns to form a recess and said gate oxide;  
       growing a thin oxide layer over said memory portion of said substrate, wherein the portion of said thin oxide layer in the lower region of said recess forms said first oxide layer and the portion of said thin oxide layer in the upper region of said recess forms said second oxide layer;  
       depositing a nitride layer over said thin oxide layer to a thickness sufficient to fill said recess; and  
       removing said nitride layer except in the region of said recess to form said ONO structures.  
     
     
       16. The method of  claim 15 , further comprising: 
       forming bit line dielectrics on said bit lines; and  
       removing said thin oxide layer from the top surface of said oxide-conductive-layer columns.  
     
     
       17. The method of  claim 16 , further comprising depositing a second conductive layer on said substrate. 
     
     
       18. The method of  claim 17 , further comprising concurrently etching said first and second conductive layers to form word lines perpendicular to and on said bit line dielectrics and said oxide-conductive-layer columns. 
     
     
       19. A method of forming a semiconductor structure, comprising: 
       forming a charge-trapping structure on a substrate; wherein said charge-trapping structure comprises:  
       (i) a first ONO structure on a first portion of said substrate;  
       (ii) a second ONO structure on a second portion of said substrate, wherein said first portion does not completely overlap said second portion; and  
       (iii) a gate oxide between said first and second ONO structures; and  
       said ONO structures comprise a nitride layer between a first oxide layer and a second oxide layer and are formed by  
       forming an oxide-conductive layer on said substrate, said oxide-conductive layer comprising a first conductive layer on a thick oxide layer;  
       within a memory portion of said substrate, removing at least a portion of said oxide-conductive layer to form oxide-conductive layer columns comprising said gate on said gate oxide;  
       implanting bit lines between said oxide-conductive layer columns;  
       forming an ONO layer within said memory portion of said substrate, said ONO layer comprising said nitride layer between said first oxide layer and said second oxide layer; and  
       removing said ONO layer except from the regions adjacent to said oxide-conductive-layer columns to form said ONO structures.  
     
     
       20. The method of  claim 19 , further comprising: 
       forming bit line dielectrics on said bit lines and said ONO structures; and  
       removing said thin oxide layer from the top surface of said oxide-conductive-layer columns.  
     
     
       21. The method of  claim 20 , further comprising depositing as second conductive layer on said substrate. 
     
     
       22. The method of  claim 21 , further comprising concurrently etching said first and second conductive layers to form word lines perpendicular to and on said bit line dielectrics and said oxide-conductive-layer columns.