Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET

Abstract

A semiconductor device including integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.

What is claimed is:  
     
       1. A semiconductor device comprising: 
       one or more insulated-gate field-effect transistor (IGFET) elements; and  
       one or more negative differential resistance field-effect transistor (NDR-FET) elements;  
       wherein at least some of said one or more IGFET elements are coupled to at least some of said one or more NDR FET elements;  
       further wherein at least some of said one or more IGFET elements and at least some of said one or more NDR-FET elements are formed by and within one or more common physical regions and/or layers associated with a single semiconductor die.  
     
     
       2. The device of  claim 1 , wherein the semiconductor device includes one or more electronic gates and/or circuits including: 
       a first type of gate and/or circuit formed exclusively of IGFET elements; and  
       a second type of gate and/or circuit formed from a combination of interconnected IGFET elements and NDR FET elements.  
     
     
       3. The device of  claim 2 , wherein the semiconductor device includes a third type of gate and/or circuit formed exclusively of NDR FET elements. 
     
     
       4. The device of  claim 2 , wherein said second type of gate and/or circuit includes a bi-stable memory cell and/or latch. 
     
     
       5. The device of  claim 4 , wherein said bi-stable latch includes an n channel IGFET element connected by a common control node in series to an n channel NDR FET element. 
     
     
       6. The device of  claim 5 , wherein said n channel IGFET element is configured as an enhancement mode device with an IGFET drain terminal and IGFET gate terminal coupled to a first voltage potential and an IFGET source terminal coupled to said common control node, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET drain terminal coupled to said common control node, and an NDR source terminal coupled to a second voltage potential. 
     
     
       7. The device of  claim 5 , wherein said n channel IGFET element is configured as an enhancement mode device with an IGFET drain terminal and IGFET gate terminal coupled to said common control node and an IFGET source terminal coupled to a first voltage potential, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET drain terminal coupled to a second voltage potential, and an NDR source terminal coupled to said common control node. 
     
     
       8. The device of  claim 5 , wherein said n channel IGFET element is configured as a depletion mode device with an IGFET source terminal and IGFET gate terminal coupled to said common control node and an IFGET drain terminal coupled to a first voltage potential, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET source terminal coupled to a second voltage potential, and an NDR drain terminal coupled to said common control node. 
     
     
       9. The device of  claim 5 , wherein said n channel IGFET element is configured as a depletion mode device with an IGFET source terminal and IGFET gate terminal coupled to a first voltage potential, and an IFGET drain terminal coupled to said common control node, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET source terminal coupled to said common control node, and an NDR drain terminal coupled to a second voltage potential. 
     
     
       10. The device of  claim 4 , further including an IGFET element configured as a transfer gate, such that a first source/drain terminal of said IGFET element is coupled to a first control node, a second source/drain terminal of said IGFET element is coupled to a second control node adapted for reading data from and/or writing data to said first control node, and an IGFET gate terminal for said IGFET element is coupled to an access signal; and further including a first NDR FET with a first NDR FET gate terminal coupled to a first bias voltage, a first NDR FET drain terminal of said first NDR FET coupled to said first control node, and a first NDR source terminal of said first NDR FET coupled to a first voltage potential; and further including a second NDR FET with a second NDR FET gate terminal coupled to a second bias voltage, a second NDR FET drain terminal of said second NDR FET coupled to a second voltage potential, and a second NDR source terminal of said second NDR FET coupled to said first control node. 
     
     
       11. The device of  claim 10 , wherein said first bias voltage and said second bias voltage are the same. 
     
     
       12. The device of  claim 10 , wherein said first bias voltage and said second voltage potential are the same. 
     
     
       13. The device of  claim 10 , wherein said second bias voltage is substantially larger than said first bias voltage. 
     
     
       14. The device of  claim 1 , wherein the semiconductor device includes a combination of logic circuits and embedded memory circuits that are implemented at least in part by NDR FET elements. 
     
     
       15. The device of  claim 1 , wherein portions of said one or more IGFET elements and said one or more NDR elements are formed at the same time during a semiconductor manufacturing process on a common substrate. 
     
     
       16. The device of  claim 15 , wherein said common substrate includes a silicon based wafer. 
     
     
       17. The device of  claim 1 , wherein IGFET source/drain regions for at least some of said one or more IGFET elements are common to and used as source/drain regions by at least some of said one or more NDR FET elements. 
     
     
       18. An semiconductor device comprising: 
       an insulated-gate field-effect transistor (IGFET) element used in a first circuit; and  
       a negative differential resistance field-effect transistor NDR-FET) element used in a second circuit;  
       said IGFET element and said NDR FET element sharing at least: (a) a common gate insulation layer; and (b) a common substrate.  
     
     
       19. The device of  claim 18 , wherein said first circuit and said second circuit are the same. 
     
     
       20. The device of  claim 19 , wherein said first circuit and said second circuit are a memory cell. 
     
     
       21. The device of  claim 18 , wherein said NDR FET and said IGFET also share a common isolation area formed in said common substrate. 
     
     
       22. The device of  claim 18 , wherein said NDR FET element includes an additional gate insulation layer in addition to said common gate insulation layer. 
     
     
       23. The device of  claim 18 , wherein said common substrate is a silicon or silicon-germanium based substrate. 
     
     
       24. The device of  claim 18 , wherein said IGFET element and said NDR FET element further share a common source/drain region. 
     
     
       25. A semiconductor wafer comprising: 
       a plurality of semiconductor die;  
       each of said plurality of semiconductor die including:  
       (a) one or more insulated-gate field-effect transistor (IGFET) elements; and  
       (b) one or more negative differential resistance field-effect transistor (NDR-FET) elements; and  
       wherein at least some of said one or more IGFET elements are coupled to at least some of said one or more NDR FET elements;  
       further wherein at least some of said one or more IGFET elements and at least some of said one or more NDR-FET elements are comprised of one or more common physical regions and/or layers associated with the semiconductor wafer.